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DAC1005D650 データシート(PDF) 1 Page - NXP Semiconductors

部品番号 DAC1005D650
部品情報  Dual 10-bit DAC, up to 650 Msps; 2쨈 4쨈 and 8쨈 interpolating
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

DAC1005D650 データシート(HTML) 1 Page - NXP Semiconductors

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1.
General description
The DAC1005D650 is a high-speed 10-bit dual-channel Digital-to-Analog Converter
(DAC) with selectable 2
×, 4× or 8× interpolating filters optimized for multi-carrier wireless
transmitters.
Thanks to its digital on-chip modulation, the DAC1005D650 allows the complex I and Q
inputs to be converted up from BaseBand (BB) to IF. The mixing frequency is adjusted
using a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator
(NCO). The phase is controlled by a 16-bit register.
Two modes of operation are available: separate data ports or a single interleaved
high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into
its original I and Q data and then latched.
The DAC1005D650 also includes a 2
×, 4× and 8× clock multiplier which provides the
appropriate internal clocks and an internal regulator to adjust the output full-scale current.
2.
Features
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2
× 4× and 8× interpolating
Rev. 01 — 28 July 2009
Product data sheet
I Dual 10-bit resolution
I IMD3: 79 dBc; fs = 640 Msps; fo =96MHz
I 650 Msps maximum update rate
I SFDR: 75 dBc; fdata = 80 MHz;
fs = 640 Msps; fo = 19 MHz; PLL on
I Selectable 2×, 4× or 8× interpolation
filters
I Typical 0.95 W power dissipation at 4×
interpolation
I Input data rate up to 160 Msps
I Power-down and Sleep modes
I Very low noise cap-free integrated PLL I Differential scalable output current from
1.6 mA to 20 mA
I 32-bit programmable NCO frequency I On-chip 1.25 V reference
I Dual-port or Interleaved data modes
I External analog offset control
(10-bit auxiliary DACs)
I 1.8 V and 3.3 V power supplies
I Internal digital offset control
I LVDS compatible clock
I Inverse (sin x) / x function
I Two’s complement or binary offset
data format
I Fully compatible SPI port
I 3.3 V CMOS input buffers
I Industrial temperature range from
−40 °Cto+85 °C


同様の部品番号 - DAC1005D650

メーカー部品番号データシート部品情報
logo
Renesas Technology Corp
DAC1005D650 RENESAS-DAC1005D650 Datasheet
412Kb / 41P
   Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
2 July 2012
DAC1005D650HW RENESAS-DAC1005D650HW Datasheet
412Kb / 41P
   Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
2 July 2012
More results

同様の説明 - DAC1005D650

メーカー部品番号データシート部品情報
logo
NXP Semiconductors
DAC1405D650 NXP-DAC1405D650 Datasheet
203Kb / 43P
   Dual 14-bit DAC, up to 650 Msps; 2쨈 4쨈 and 8쨈 interpolating
Rev. 01-4 May 2009
DAC1205D650 NXP-DAC1205D650 Datasheet
203Kb / 42P
   Dual 12-bit DAC, up to 650 Msps; 2쨈 4쨈 and 8쨈 interpolating
Rev. 01-28 July 2009
DAC1408D650 NXP-DAC1408D650 Datasheet
360Kb / 88P
   Dual 14-bit DAC, up to 650 Msps, 2쨈 and 4쨈 interpolating with JESD204A interface
Rev. 01-26 May 2009
logo
Renesas Technology Corp
DAC1005D650 RENESAS-DAC1005D650 Datasheet
412Kb / 41P
   Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
2 July 2012
DAC1205D650 RENESAS-DAC1205D650 Datasheet
412Kb / 41P
   Dual 12-bit DAC, up to 650 Msps; 2x4x and 8x interpolating
2 July 2012
logo
Integrated Device Techn...
DAC1405D650 IDT-DAC1405D650 Datasheet
409Kb / 41P
   Dual 14-bit DAC, up to 650 Msps; 2?? 4??and 8??interpolating
logo
Renesas Technology Corp
DAC1405D650 RENESAS-DAC1405D650 Datasheet
413Kb / 41P
   Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
2 July 2012
DAC1005D750 RENESAS-DAC1005D750 Datasheet
418Kb / 43P
   Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating
2 July 2012
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NXP Semiconductors
DAC1408D650_1008 NXP-DAC1408D650_1008 Datasheet
2Mb / 98P
   Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
Rev. 02-11 August 2010
logo
Renesas Technology Corp
DAC1008D650 RENESAS-DAC1008D650 Datasheet
631Kb / 96P
   Dual 10-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface
2 July 2012
More results


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