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UC1849 データシート(PDF) 9 Page - Texas Instruments |
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UC1849 データシート(HTML) 9 Page - Texas Instruments |
9 / 11 page 9 at 7MHz, where the phase margin begins to roll off. See Figure 8 for typical Bode plot. The gain of the differential current sense amplifier (CSGAIN) is calculated by knowing the maximum load current. The maximum voltage across the shunt resistor (RS) divided by RS is the maximum load current. By amplifying the voltage across RS, VRS, to be equal to the voltage error amplifier Voh, the current control loop keeps the load from exceeding its current limit. Voh is set at 3.0V if ILIM is connected to VREF. The maximum current limit clamp can be reduced by reducing the voltage at ILIM to less than 3.0V as described in the ILIM pin description. VRS Max ILOAD VILIM VRS. The current error amplifier (CEA) also needs its loop compensated by the user with the same criteria as the current sense amplifier. This amplifier is essentially the same wide bandwidth amplifier without the input offset voltage trim. The zero crossing can also be approximate- ly calculated with Equation 3. The gain bandwidth of the current loop is optimized by matching the inductor downslope (Vo/L) to the oscillator ramp slope (Vs · fs). Subharmonic oscillation problems are avoided by keep- ing the amplified inductor downslope less than the oscil- lator ramp slope. The following equation determines the current error amplifier gain (GCA): Vs · fs (Vo/L) · RS · CSGAIN where CSGAIN and RS are defined by equations 4 and 5, Vs is the oscillator peak to peak voltage, fs is the oscillator frequency, Vo is the output voltage, and L is the inductance. Additional Information about average current mode con- trol can be found in Unitrode Application Note U-140. Design Example: Figure 9 is an open loop test that lets the user test the circuit blocks discussed without having to build an entire control loop. The pulse width can be varied by either the VADJ or the VISENSE inputs. Figure 10 shows an isolated power supply using the UC1849 sec- ondary side average current mode controller. UC1849 UC2849 UC3849 CIRCUIT BLOCK DESCRIPTION (cont.) β ∅m − Figure 8. Current Sense Amplifier and Current Error Amplifier Bode Plot (5) CSGAIN = (6) GCA = ; (4) RS = Figure 9. Open Loop Circuit UDG-94115-1 |
同様の部品番号 - UC1849 |
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同様の説明 - UC1849 |
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