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UC1879 データシート(PDF) 4 Page - Texas Instruments |
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UC1879 データシート(HTML) 4 Page - Texas Instruments |
4 / 7 page 4 UC1879 UC2879 UC3879 Note 1. Phase shift percentage (0% = 0 °, 100% = 180°)isde- fined as θ= 200 T Φ % where θ is the phase shift, and Φ and T are defined in Figure 1. At 0% phase shift, Φ is the output skew. Note 2. Delay time is defined as: delay T duty cycle =• 1 2 where T is defined in Figure 1. Note 3. Ramp offset voltage has a temperature coeffecient of about –4mV/ °C. Note 4. The zero phase shift voltage is the voltage measured at COMP which forces zero phase shift. This condition corre- sponds to zero effective output power. Zero phase shift voltage has a temperature coeffecient of about –2mV/ °C. Note 5. Delay time can be programmed via resistors from the delay set pins to ground. () Delay Time RDELAY =• • − 089 10 .sec The recommended range for RDELAY is 1.9k to 10k. Figure 1. Phase Shift, Output Skew & Delay Time Definitions Duty Cycle = t T Period=T TDHL(A to C) = TDHL(B to D) = Φ ELECTRICAL CHARACTERISTICS Unless specified; VC = VIN = VUVSEL =12V, CT = 470pF, RT = 9.53k, RDELSETA-B = RDELSEC-D = 4.8k, CDELSETA-B =CDELSETC-D = 0.01µF, TA =TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Ramp Peak Voltage 2.8 2.9 3.2 V Current Limit Input Bias VCS = 3.0V 2 10 µA Threshold Voltage 2.35 2.5 2.65 V Delay to OUTA, B, C, D 160 300 ns Cycle-by-Cycle Current Limit Input Bias VCS = 2.2V 2 10 µA Threshold Voltage 1.85 2 2.15 V Delay to Output Zero Phase 110 300 ns Soft Start/Reset Delay Charge Current VSS = 0.5V –20 –9 –3 µA Discharge Current VSS = 1V 120 230 µA Restart Threshold 4.3 4.7 V Discharge Level 300 mV Output Drivers Output Low Level IOUT = 10mA 0.3 0.4 V Output High Level IOUT = –10mA, Referenced to VC 2.2 3 V Delay Set (Note 5) Delay Time RDELSETA-B =RDELSETC-D = 4.8k 300 430 600 ns Delay Time RDELSETA-B =RDELSETC-D= 1.9k 130 170 250 ns Zero Delay VDELSETA-B =VDELSETC-D =5V 5 ns |
同様の部品番号 - UC1879 |
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同様の説明 - UC1879 |
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