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STK11C68-5 (SMD5962-92324)
Document Number: 001-51001 Rev. *A
Page 8 of 15
Figure 9. SRAM Write Cycle 2: CE and OE Controlled [7, 8]
SRAM Write Cycle
Parameter
Description
35 ns
45 ns
55 ns
Unit
Min
Max
Min
Max
Min
Max
Cypress
Parameter
Alt
tWC
tAVAV
Write Cycle Time
35
45
55
ns
tPWE
tWLWH, tWLEH Write Pulse Width
25
30
45
ns
tSCE
tELWH, tELEH Chip Enable To End of Write
25
30
45
ns
tSD
tDVWH, tDVEH Data Setup to End of Write
12
15
30
ns
tHD
tWHDX, tEHDX Data Hold After End of Write
0
0
0
ns
tAW
tAVWH, tAVEH Address Setup to End of Write
25
30
45
ns
tSA
tAVWL, tAVEL Address Setup to Start of Write
0
0
0
ns
tHA
tWHAX, tEHAX Address Hold After End of Write
0
0
0
ns
tHZWE
[6,7]
tWLQZ
Write Enable to Output Disable
13
15
35
ns
tLZWE
[6]
tWHQX
Output Active After End of Write
5
5
5
ns
Switching Waveforms
Figure 8. SRAM Write Cycle 1: WE Controlled [7, 8]
Notes
7. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
8. CE or WE must be greater than VIH during address transitions.
tWC
tSCE
tHA
tAW
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
tWC
ADDRESS
tSA
tSCE
tHA
tAW
tPWE
tSD
tHD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
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