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AD7193 データシート(PDF) 11 Page - Analog Devices |
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AD7193 データシート(HTML) 11 Page - Analog Devices |
11 / 56 page AD7193 Rev. A | Page 11 of 56 Pin No. Mnemonic Description 15 AIN5 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN6 or as a pseudo differential input when used with AINCOM. 16 AIN6 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN5 or as a pseudo differential input when used with AINCOM. 17 AIN7 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN8 or as a pseudo differential input when used with AINCOM. 18 AIN8 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN7 or as a pseudo differential input when used with AINCOM. 19 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. 20 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. 21 BPDSW Bridge Power-Down Switch to AGND. 22 AGND Analog Ground Reference Point. 23 DGND Digital Ground Reference Point. 24 AVDD Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with AVDD at 5 V or vice versa. 25 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V with DVDD at 5 V or vice versa. 26 SYNC Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7193 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to DVDD. 27 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. 28 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register. |
同様の部品番号 - AD7193 |
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同様の説明 - AD7193 |
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