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FIN210ACMLX データシート(PDF) 3 Page - Fairchild Semiconductor |
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FIN210ACMLX データシート(HTML) 3 Page - Fairchild Semiconductor |
3 / 17 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN210AC • Rev. 1.0.1 3 FIN210AC (Deserializer DIRI=0) Pin Descriptions Pin Name Description 0 Deserializer DIRI Control to determine serializer or deserializer configuration. 1 Serializer 0 Internal termination used XTERM Control to determine if using internal or external termination 1 External termination required on CKSI & DSI S0 Signals used to define the edge rate of parallel I/O. See Table 2 Deserializer (DIRI=0) Control Pin. S1 Signals used to define the edge rate of parallel I/O. See Table 2 Deserializer (DIRI=0) Control Pin. PWS0 Configure CKP pulse width. See Table 2 Deserializer (DIRI=0) Control Pin. PWS1 Configure CKP pulse width. See Table 2 Deserializer (DIRI=0) Control Pin. /ENZ High-Z or known state outputs during power down See Table 5 Deserializer (DIRI=0) Control Pin. DP[1:10] LV-CMOS parallel data output. (N/C if not used) CKP LV-CMOS word clock output or Pixel clock output. DSI+ DSI- CTL Differential serial input data signals. DSI+: Positive signal; DSI-: Negative signal. CKSI+ CKSI- CTL Differential deserializer input bit clock. CKSI+: Positive signal; CKSI-: Negative signal. CKSO+ CKSO- CTL Differential serializer output bit clock. CKSO+: Positive signal; CKSO-: Negative signal. No connect unless in “clock pass-through” mode. CKREF LV-CMOS clock input and PLL reference. No connect unless in “clock pass-through” mode. STROBE LV-CMOS strobe input for latching data into the serializer. No connect unless in “clock pass-through” mode. /DIRO LV-CMOS Output. Inversion of DIRI in normal operation. No connect if not used. VDDP Power supply for parallel I/O. (All VDDP pins must be connected to VDDP) VDDS Power supply for serial I/O. VDDA Power supply for core. GND All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 28, 29, GND PAD must be grounded. N/C No connect. BGA: G1, F2; MLP: 10, 11; (Do not connect to GND or VDD) Note: 2. 0=GND; 1=VDDP FIN210AC (Deserializer DIRI=0) Pin Configurations GND DP[2] CKREF DP[5] DP[1] STROBE DP[3] VDDP GND PWS1 1 A 3456 2 B C D E F G DP[4] DP[6] /DIRO CKP CKSO+ CKSO- DP[7] DSI+ DSI- DP[8] DP[9] VDDS CKSI+ CKSI- DP[10] VDDA DIRI PWS0 S1 S0 /ENZ N/C N/C N/C N/C XTRM N/C N/C N/C N/C N/C N/C DESERIALIZER GND PAD DP[4] CKSO+ CKSO- DSI- DSI+ CKSI- CKSI+ DIRI VDDS 1 DP[5] 2 4 DP[6] VDDP 3 CKP 5 DP[7] 6 DP[8] 7 DP[9] 8 20 21 19 23 18 17 22 24 42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View) 32-pin MLP, 5mm x 5mm, .5mm pitch (Top View) (Center pad must be grounded) Figure 3. FIN210AC (Deserializer DIRI=0) Pin Assignments (Top View) |
同様の部品番号 - FIN210ACMLX |
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同様の説明 - FIN210ACMLX |
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