MC-45D32CC721KFA-C75 datasheet(6/16 Pages) ELPIDA

部品番号	MC-45D32CC721KFA-C75

部品情報	32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE

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Preliminary Data Sheet E0033N10

6

DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)

Parameter

Symbol

Test condition

/CAS

latency

Grade

MIN.

MAX.

Unit

Notes

-C75

TBD

mA

Operating current

(ACT-PRE)

IDD0

tRC = tRC(MIN.), tCK = tCK (MIN.), One bank,

Active-precharge, DQ, DM and DQS

inputs changing twice per clock cycle,

Address and control inputs changing

once per clock cycle

-C80

TBD

CL = 2

-C75

TBD

mA

1

-C80

TBD

CL = 2.5 -C75

TBD

Operating current

(ACT-READ-PRE)

IDD1

tRC = tRC(MIN.), tCK = tCK (MIN.), One

bank, Active-read-precharge,

IO = 0 mA, Burst length = 2,

Address and control inputs

changing once per clock cycle

-C80

TBD

Precharge power down

standby current

IDD2P

CKE

≤ VIL(MAX.), tCK = tCK(MIN.),

All banks idle, Power down mode

TBD

mA

Idle standby current

IDD2N

CKE

≥ VIH(MIN.), tCK = tCK(MIN.), /CS ≥ VIH(MIN.),

All banks idle, Address and other control inputs

changing once per clock cycle

TBD

mA

Active power down

standby current

IDD3P

CKE

≤ VIL(MAX.), tCK = tCK(MIN.), One bank active,

Power down mode

TBD

mA

Active standby current

IDD3N

/CS

≥ VIH(MIN.), CKE ≥ VIH(MIN.), tCK = tCK(MIN.), tRC =

tRAS(MAX.), One bank, Active-precharge, DQ, DM

and DQS inputs changing twice per clock

cycle, Address and other control inputs

changing once per clock cycle

TBD

mA

CL = 2

-C75

TBD

mA

2

-C80

TBD

CL = 2.5 -C75

TBD

Operating current

(Burst read)

IDD4R

tCK = tCK(MIN.), Continuous burst

read, Burst length = 2, IO =

0mA, One bank active,

Address and control inputs

changing once per clock cycle

-C80

TBD

CL = 2

-C75

TBD

mA

2

-C80

TBD

CL = 2.5 -C75

TBD

Operating current

(Burst write)

IDD4W

tCK = tCK(MIN.), Continuous burst

write, Burst length = 2, One

bank active, Address and

control inputs changing once

per clock cycle

-C80

TBD

CBR (Auto) refresh current

IDD5

tRFC = tRFC(MIN.)

-C75

TBD

mA

-C80

TBD

Self refresh current

IDD6

CKE

≤ 0.2 V

TBD

mA

Notes 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open.

2. IDD4R and IDD4W depend on output loading and cycle rates. Specified values are obtained with the output

open.

DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)

Parameter

Symbol

Test condition

MIN.

MAX.

Unit Notes

Input leakage current

II(L)

VI = 0 to 3.6 V, all other pins not under test = 0 V

TBD

µA

Output leakage current

IO(L)

DOUT is disabled, VO = 0 to VDDQ + 0.3 V

TBD

µA

Output high current

IOH

VOUT = VDDQ

− 0.43 V

TBD

mA

Output low current

IOL

VOUT = 0.35 V

TBD

mA

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