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FM23MLD16 データシート(PDF) 2 Page - Ramtron International Corporation

部品番号 FM23MLD16
部品情報  8Mbit F-RAM Memory
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メーカー  RAMTRON [Ramtron International Corporation]
ホームページ  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM23MLD16 データシート(HTML) 2 Page - Ramtron International Corporation

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FM23MLD16 - 512Kx16 FRAM (multi die)
Rev. 1.0
Dec. 2008
Page 2 of 13
Figure 1. Block Diagram
Pin Description
Pin Name
Type
Pin Description
A(18:0)
Input
Address inputs: The A(17:0) address lines select one of 262,144 words in each of the F-
RAM die. A18 selects one of the two die. The lowest two address lines A(1:0) may be
used for page mode read and write operations.
/CE1, CE2
Input
Chip Enable inputs: The device is selected and a new memory access begins on the
falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low). The
entire address is latched internally at this point.
/WE
Input
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM23MLD16 to write the data on the DQ bus to the F-RAM array. The falling edge of
/WE latches a new column address for page mode write cycles.
/OE
Input
Output Enable: When /OE is low, the FM23MLD16 drives the data bus when valid read
data is available. Deasserting /OE high tri-states the DQ pins.
DQ(15:0)
I/O
Data: 16-bit bi-directional data bus for accessing the F-RAM array.
/UB
Input
Upper Byte Select: Enables DQ(15:8) pins during reads and writes. These pins are hi-Z
if /UB is high.
/LB
Input
Lower Byte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z
if /LB is high.
VDD
Supply
Supply Voltage: 3.3V
VSS
Supply
Ground


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