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FM24CL32-GTR データシート(PDF) 9 Page - Ramtron International Corporation |
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FM24CL32-GTR データシート(HTML) 9 Page - Ramtron International Corporation |
9 / 12 page FM24CL32 Rev. 1.0 May 2009 Page 9 of 12 AC Parameters (TA = -40° C to + 85° C, VDD =2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz 1 tLOW Clock Low Period 4.7 1.3 0.6 µs tHIGH Clock High Period 4.0 0.6 0.4 µs tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs tBUF Bus Free Before New Transmission 4.7 1.3 0.5 µs tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 µs tHD:DAT Data In Hold 0 0 0 ns tSU:DAT Data In Setup 250 100 100 ns tR Input Rise Time 1000 300 300 ns 2 tF Input Fall Time 300 300 100 ns 2 tSU:STO Stop Condition Setup 4.0 0.6 0.25 µs tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to 1 MHz. 2 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3V) Symbol Parameter Max Units Notes CI/O Input/Output Capacitance (SDA) 8 pF 1 CIN Input Capacitance 6 pF 1 Notes 1 This parameter is periodically sampled and not 100% tested. Power Cycle Timing (TA = -40° C to +85° C) Symbol Parameter Min Max Units Notes tVR VDD Rise Time 50 - µs/V 1, 2 tVF VDD Fall Time 100 - µs/V 1, 2 tPU Power Up (VDD min) to First Access (Start condition) 5 - ms tPD Last Access (Stop condition) to Power Down (VDD min) 0 - µs Notes 1. Slope measured at any point on VDD waveform. 2. This parameter is characterized and not 100% tested. |
同様の部品番号 - FM24CL32-GTR |
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同様の説明 - FM24CL32-GTR |
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