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AM1806BZWTD4 データシート(PDF) 1 Page - Texas Instruments |
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AM1806BZWTD4 データシート(HTML) 1 Page - Texas Instruments |
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1 / 241 page  AM1806 www.ti.com SPRS658 – FEBRUARY 2010 AM1806 ARM Microprocessor Check for Samples: AM1806 1 AM1806 ARM Microprocessor 1.1 Features 12 via software to save power • 375/456-MHz ARM926EJ-S™ RISC MPU • Register 30 of each PRU is exported from • Enhanced Direct-Memory-Access Controller 3 the subsystem in addition to the normal (EDMA3): R31 output of the PRU cores. – 2 Channel Controllers – Standard power management mechanism – 3 Transfer Controllers • Clock gating – 64 Independent DMA Channels • Entire subsystem under a single PSC – 16 Quick DMA Channels clock gating domain – Programmable Transfer Burst Size – Dedicated interrupt controller • 1.8V or 3.3V LVCMOS IOs (except for USB and – Dedicated switched central resource DDR2 interfaces) • USB 2.0 OTG Port With Integrated PHY (USB0) • Two External Memory Interfaces: – USB 2.0 High-/Full-Speed Client – EMIFA – USB 2.0 High-/Full-/Low-Speed Host • NOR (8-/16-Bit-Wide Data) – End Point 0 (Control) • NAND (8-/16-Bit-Wide Data) – End Points 1,2,3,4 (Control, Bulk, Interrupt or • 16-Bit SDRAM With 128 MB Address ISOC) Rx and Tx Space • One Multichannel Audio Serial Port: – DDR2/Mobile DDR Memory Controller – Transmit/Receive Clocks • 16-Bit DDR2 SDRAM With 512 MB – Two Clock Zones and 16 Serial Data Pins Address Space or – Supports TDM, I2S, and Similar Formats • 16-Bit mDDR SDRAM With 256 MB Address Space – DIT-Capable • Three Configurable 16550 type UART Modules: – FIFO buffers for Transmit and Receive – With Modem Control Signals • Two Multichannel Buffered Serial Ports: – 16-byte FIFO – Transmit/Receive Clocks – 16x or 13x Oversampling Option – Two Clock Zones and 16 Serial Data Pins • Two Serial Peripheral Interfaces (SPI) Each – Supports TDM, I2S, and Similar Formats With Multiple Chip-Selects – AC97 Audio Codec Interface • Two Multimedia Card (MMC)/Secure Digital (SD) – Telecom Interfaces (ST-Bus, H100) Card Interface with Secure Data I/O (SDIO) – 128-channel TDM Interfaces – FIFO buffers for Transmit and Receive • Two Master/Slave Inter-Integrated Circuit (I2C • Video Port Interface (VPIF): Bus™) – Two 8-bit SD (BT.656), Single 16-bit or Single • One Host-Port Interface (HPI) With 16-Bit-Wide Raw (8-/10-/12-bit) Video Capture Channels Muxed Address/Data Bus For High Bandwidth – Two 8-bit SD (BT.656), Single 16-bit Video • Programmable Real-Time Unit Subsystem Display Channels (PRUSS) • Universal Parallel Port (uPP): – Two Independent Programmable Realtime – High-Speed Parallel Interface to FPGAs and Unit (PRU) Cores Data Converters • 32-Bit Load/Store RISC architecture – Data Width on Each of Two Channels is 8- to • 4K Byte instruction RAM per core 16-bit Inclusive • 512 Bytes data RAM per core – Single Data Rate or Dual Data Rate Transfers • PRU Subsystem (PRUSS) can be disabled 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 ARM926EJ-S is a trademark of ARM Limited. ADVANCE INFORMATION concerns new products in the sampling Copyright © 2010, Texas Instruments Incorporated or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. |
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同様の説明 - AM1806BZWTD4 |
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