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BU1574GUW データシート(PDF) 9 Page - Rohm |
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BU1574GUW データシート(HTML) 9 Page - Rohm |
9 / 13 page Technical Note 9/12 BU1574GUW www.rohm.com 2009.06 - Rev.A © 2009 ROHM Co., Ltd. All rights reserved. 9. I 2C Interface format The slave address is 42h when I2CDEV0 = 0 and 43h when I2CDEV0 = 1. When both of the write and read accesses are respectively executed successively 2 times or more, the sub-address is automatically incremented. SDA SDC Data transfer 1-7 8 S 1-789 STOP condition 91-7 8 9 P ACK ACK ACK Sub address Data Slave address R/W START condition Write sequence Read sequence S = START condition A(S) = acknowledge by slave A(S) = not acknowledge by slave P = STOP condition A(M) = acknowledge by master A(M) = not acknowledge by master S Slave address (42h or 43h) W (0) A(S) Sub address A(S) Data A(S) Data A(S) Data A(S)/ A(S) A(M)/ A(M) P P S Slave address (42h or 43h) A(S) Sub address A(S) S Slave address (42h or 43h) W (0) R (1) A(M) Data A(S) Data Fig.9 I 2C Interface format ● Timing chart 1. Data input interface timing CAMVSI CAMHSI CAMDI0 -CAMDI7 CAMCKI (CKPOL-“0”) CAMCKI (CKPOL-“1”) tDS tDH Fig.10 Data input interface timing Symbol Descriptions MIN TYP MAX Unit tDS Setup time to CAMCKI rising / falling edge 8 - - ns tDH Hold time to CAMCKI rising / falling edge 8 - - ns |
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同様の説明 - BU1574GUW |
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