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74ABT544PW データシート(PDF) 3 Page - NXP Semiconductors |
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74ABT544PW データシート(HTML) 3 Page - NXP Semiconductors |
3 / 15 page 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 3 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description Fig 4. Pin configuration 74ABT544 VCC OEBA EBA A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 EAB LEAB GND OEAB 001aac755 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 LEBA Table 2. Pin description Symbol Pin Description LEBA 1 B-to-A latch enable input (active LOW) OEBA 2 B-to-A output enable input (active LOW) A0 to A7 3, 4, 5, 6, 7, 8, 9, 10 data input or output EAB 11 A-to-B enable input (active LOW) GND 12 ground (0 V) OEAB 13 A-to-B output enable input (active LOW) LEAB 14 A-to-B latch enable input (active LOW) B0 to B7 22, 21, 20, 19, 18, 17, 16, 15 data input or output EBA 23 B-to-A enable input (active LOW) VCC 24 positive supply voltage |
同様の部品番号 - 74ABT544PW |
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同様の説明 - 74ABT544PW |
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