74ABT823D datasheet(7/17 Pages) NXP

部品番号	74ABT823D

部品情報	9-bit D-type flip-flop with reset and enable; 3-state

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74ABT823_3

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Product data sheet

Rev. 03 — 23 March 2010

7 of 17

NXP Semiconductors

74ABT823

9-bit D-type flip-flop with reset and enable; 3-state

[1]

For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

[2]

This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V ± 10 %

a transition time of up to 100

μs is permitted.

[3]

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

[4]

This is the increase in supply current for each input at 3.4 V.

10. Dynamic characteristics

ΔI

CC

additional supply

current

per input pin; VCC = 5.5 V;

one input at 3.4 V;

other inputs at VCC or GND

[4]

-

0.5

1.5

-

1.5

mA

CI

input capacitance

VI = 0 V or VCC

-

4

-

pF

CO

output capacitance

outputs disabled; VO = 0 V or VCC

-

7

-

pF

Table 6.

Static characteristics …continued

Symbol

Parameter

Conditions

25

°C

−40 °C to +85 °C Unit

Min

Typ

Max

Min

Max

Table 7.

Dynamic characteristics

GND = 0 V; for test circuit, see Figure 9.

Symbol Parameter

Conditions

25

°C; V

CC = 5.0 V

−40 °C to +85 °C;

VCC = 5.0 V ± 0.5 V

Unit

Min

Typ

Max

Min

Max

fmax

maximum

frequency

see Figure 5

125

200

-

125

-

MHz

tPLH

LOW to HIGH

propagation delay

CP to Qn, see Figure 5

2.1

4.3

5.9

2.1

6.8

ns

tPHL

HIGH to LOW

propagation delay

CP to Qn, see Figure 5

2.2

4.4

6.1

2.2

6.7

ns

MR to Qn, see Figure 6

2.0

4.1

6.3

2.0

7.1

ns

tPZH

OFF-state to HIGH

propagation delay

OE to Qn; see Figure 8

1.0

3.0

4.5

1.0

5.3

ns

tPZL

OFF-state to LOW

propagation delay

OE to Qn; see Figure 8

2.2

4.1

5.6

2.2

6.3

ns

tPHZ

HIGH to OFF-state

propagation delay

OE to Qn; see Figure 8

2.7

4.8

6.2

2.7

6.9

ns

tPLZ

LOW to OFF-state

propagation delay

OE to Qn; see Figure 8

2.5

5.0

6.4

2.5

6.9

ns

tsu(H)

set-up time HIGH

Dn to CP; see Figure 7

2.1

0.5

-

2.1

-

ns

CE to CP; see Figure 7

+2.0

−0.5

-

+2.0

-

ns

tsu(L)

set-up time LOW

Dn to CP; see Figure 7

2.1

0.2

-

2.1

-

ns

CE to CP; see Figure 7

3.3

1.5

-

3.3

-

ns

th(H)

hold time HIGH

CP to Dn; see Figure 7

1.3

0.0

-

1.3

-

ns

CP to CE; see Figure 7

+1.0

−1.4

-

+1.0

-

ns

th(L)

hold time LOW

CP to Dn; see Figure 7

+1.3

−0.3

-

+1.3

-

ns

CP to CE; see Figure 7

2.0

0.7

-

2.0

-

ns

tWH

pulse width HIGH

CP; see Figure 5

2.9

1.9

-

2.9

-

ns

同様の部品番号 - 74ABT823D

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NXP Semiconductors	74ABT823D	77Kb / 7P	9-bit D-type flip-flop with reset and enable 3-State 1995 Sep 06
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