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74HCT9046APW データシート(PDF) 9 Page - NXP Semiconductors |
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74HCT9046APW データシート(HTML) 9 Page - NXP Semiconductors |
9 / 43 page 74HCT9046A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 15 September 2009 9 of 43 NXP Semiconductors 74HCT9046A PLL with band gap controlled VCO 8.3.2 Phase Comparator 2 (PC2) This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty cycles of SIG_IN and COMP_IN are not important. PC2 comprises two D-type flip-flops, control gating and a 3-state output stage with sink and source transistors acting as current sources, henceforth called charge pump output of PC2. The circuit functions as an up-down counter (see Figure 4) where SIG_IN causes an up-count and COMP_IN a down count. The current switch charge pump output allows a virtually ideal performance of PC2, due to appliance of some pulse overlap of the up and down signals, see Figure 8a. The pump current Icp is independent from the supply voltage and is set by the internal band gap reference of 2.5 V. Where Rbias is the external bias resistor between pin RB and ground. The current and voltage transfer function of PC2 are shown in Figure 9. The phase comparator gain is: Fig 7. Typical waveforms for PLL using phase comparator 1; loop-locked at f0 mbd100 PC1_OUT VCO_IN VCC GND VCO_OUT COMP_IN SIGN_IN C1A C1B VC1A VC1B I cp 17 2.5 R bias ------------ A () × = K P I cp 2 π ---------- Ar ⁄ () = |
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