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AM1806BZWTA4 データシート(PDF) 1 Page - Texas Instruments

部品番号 AM1806BZWTA4
部品情報  AM1806 ARM Microprocessor
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
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AM1806
www.ti.com
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
AM1806 ARM Microprocessor
Check for Samples: AM1806
1
AM1806 ARM Microprocessor
1.1
Features
12
– With Modem Control Signals
• Highlights
– 16-byte FIFO
– 375/456-MHz ARM926EJ-S™ RISC Core
– 16x or 13x Oversampling Option
– ARM9 Memory Architecture
• Two Serial Peripheral Interfaces (SPI) Each
– Programmable Real-Time Unit Subsystem
With Multiple Chip-Selects
– Enhanced Direct-Memory-Access Controller
• Two Multimedia Card (MMC)/Secure Digital (SD)
3 (EDMA3)
Card Interface with Secure Data I/O (SDIO)
– Two External Memory Interfaces
Interfaces
– Three Configurable 16550 type UART
• Two Master/Slave Inter-Integrated Circuit (I2C
Modules
Bus™)
– Two Serial Peripheral Interfaces (SPI)
• One Host-Port Interface (HPI) With 16-Bit-Wide
– Multimedia Card (MMC)/Secure Digital (SD)
Muxed Address/Data Bus For High Bandwidth
Card Interface with Secure Data I/O (SDIO)
• Programmable Real-Time Unit Subsystem
– Two Master/Slave Inter-Integrated Circuit
(PRUSS)
– USB 2.0 OTG Port With Integrated PHY
– Two Independent Programmable Realtime
– One Multichannel Audio Serial Port
Unit (PRU) Cores
– Three 64-Bit General-Purpose Timers
32-Bit Load/Store RISC architecture
– One 64-bit General-Purpose/Watchdog Timer
4K Byte instruction RAM per core
– TwoEnhanced Pulse Width Modulators
512 Bytes data RAM per core
– Three 32-Bit Enhanced Capture Modules
PRU Subsystem (PRUSS) can be disabled
• 375/456-MHz ARM926EJ-S™ RISC MPU
via software to save power
• Enhanced Direct-Memory-Access Controller 3
Register 30 of each PRU is exported from
(EDMA3):
the subsystem in addition to the normal
– 2 Channel Controllers
R31 output of the PRU cores.
– 3 Transfer Controllers
– Standard power management mechanism
– 64 Independent DMA Channels
Clock gating
– 16 Quick DMA Channels
Entire subsystem under a single PSC
clock gating domain
– Programmable Transfer Burst Size
– Dedicated interrupt controller
• 1.8V or 3.3V LVCMOS IOs (except for USB and
DDR2 interfaces)
– Dedicated switched central resource
• Two External Memory Interfaces:
• USB 2.0 OTG Port With Integrated PHY (USB0)
– EMIFA
– USB 2.0 High-/Full-Speed Client
NOR (8-/16-Bit-Wide Data)
– USB 2.0 High-/Full-/Low-Speed Host
NAND (8-/16-Bit-Wide Data)
– End Point 0 (Control)
16-Bit SDRAM With 128 MB Address
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
Space
ISOC) Rx and Tx
– DDR2/Mobile DDR Memory Controller
• One Multichannel Audio Serial Port:
16-Bit DDR2 SDRAM With 512 MB
– Transmit/Receive Clocks
Address Space or
– Two Clock Zones and 16 Serial Data Pins
16-Bit mDDR SDRAM With 256 MB
– Supports TDM, I2S, and Similar Formats
Address Space
– DIT-Capable
• Three Configurable 16550 type UART Modules:
– FIFO buffers for Transmit and Receive
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
ARM926EJ-S is a trademark of ARM Limited.
ADVANCE INFORMATION concerns new products in the sampling
Copyright © 2010, Texas Instruments Incorporated
or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.


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