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ADF7021-VBCPZ データシート(PDF) 9 Page - Analog Devices |
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ADF7021-VBCPZ データシート(HTML) 9 Page - Analog Devices |
9 / 60 page ADF7021-V Rev. 0 | Page 9 of 60 DIGITAL SPECIFICATIONS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments TIMING INFORMATION Chip Enabled to Regulator Ready 50 μs CREG[1:4] = 100 nF Chip Enabled to Tx Mode 32-bit register write time = 50 μs TCXO Reference 1 ms Depends on VCO settling XTAL 2 ms Depends on VCO settling Chip Enabled to Rx Mode 32-bit register write time = 50 μs, IF filter coarse calibration only TCXO Reference 1.2 ms Depends on VCO settling XTAL 2.2 ms Depends on VCO settling Tx-to-Rx Turnaround Time AGC settling + (5 × tBIT) ms Time to synchronized data output; includes AGC settling (three AGC levels) and CDR synchronization; tBIT = data bit period; AFC settling not included LOGIC INPUTS Input High Voltage, VINH 0.7 × VDD V Input Low Voltage, VINL 0.2 × VDD V Input Current, IINH/IINL ±1 μA Input Capacitance, CIN 10 pF Control Clock Input 50 MHz LOGIC OUTPUTS Output High Voltage, VOH VDD2 − 0.4 V IOH = 500 μA Output Low Voltage, VOL 0.4 V IOL = 500 μA CLKOUT Rise/Fall Time 5 ns CLKOUT Load 10 pF |
同様の部品番号 - ADF7021-VBCPZ |
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同様の説明 - ADF7021-VBCPZ |
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