N02L63W3AT5IT datasheet(5/11 Pages) ONSEMI

部品番号	N02L63W3AT5IT

部品情報	2Mb Ultra-Low Power Asynchronous CMOS SRAM 128K 횞 16bit

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メーカー	ONSEMI [ON Semiconductor]

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5 / 11 page

Rev.

15 | Page 5 of 11 | www.onsemi.com

N02L63W3A

Power Savings with Page Mode Operation (WE = VIH)

Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal

organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power

saving feature.

The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open

and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant

bits and addressing the 16 words within the open page, power is reduced to the page mode value which is

considerably lower than standard operating currents for low power SRAMs.

Page Address (A4 - A16 )

LB, UB

OE

CE

Word Address (A0 - A3)

Open page

Word 1

Word 2

Word 16

...

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	N02L63W2AB25I	659Kb / 11P	2Mb Ultra-Low Power Asynchronous CMOS SRAM 128K 횞 16 bit July 2008 - Rev. 9
	N02L63W2AB25IT	659Kb / 11P	2Mb Ultra-Low Power Asynchronous CMOS SRAM 128K 횞 16 bit July 2008 - Rev. 9
	N02L63W2AB5I	659Kb / 11P	2Mb Ultra-Low Power Asynchronous CMOS SRAM 128K 횞 16 bit July 2008 - Rev. 9
	N02L63W2AB5IT	659Kb / 11P	2Mb Ultra-Low Power Asynchronous CMOS SRAM 128K 횞 16 bit July 2008 - Rev. 9

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