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LM3S9L97-IQN50-C1 データシート(PDF) 3 Page - Texas Instruments |
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LM3S9L97-IQN50-C1 データシート(HTML) 3 Page - Texas Instruments |
3 / 1219 page Table of Contents Revision History ............................................................................................................................. 36 About This Document .................................................................................................................... 41 Audience .............................................................................................................................................. 41 About This Manual ................................................................................................................................ 41 Related Documents ............................................................................................................................... 41 Documentation Conventions .................................................................................................................. 42 1 Architectural Overview .......................................................................................... 44 1.1 Functional Overview ...................................................................................................... 46 1.1.1 ARM Cortex™-M3 ......................................................................................................... 46 1.1.2 On-Chip Memory ........................................................................................................... 48 1.1.3 Serial Communications Peripherals ................................................................................ 49 1.1.4 System Integration ........................................................................................................ 55 1.1.5 Advanced Motion Control ............................................................................................... 61 1.1.6 Analog .......................................................................................................................... 63 1.1.7 JTAG and ARM Serial Wire Debug ................................................................................ 64 1.1.8 Packaging and Temperature .......................................................................................... 65 1.2 Target Applications ........................................................................................................ 65 1.3 High-Level Block Diagram ............................................................................................. 66 1.4 Additional Features ....................................................................................................... 68 1.4.1 Memory Map ................................................................................................................ 68 1.4.2 Hardware Details .......................................................................................................... 68 2 ARM Cortex-M3 Processor Core ........................................................................... 69 2.1 Block Diagram .............................................................................................................. 70 2.2 Functional Description ................................................................................................... 70 2.2.1 Programming Model ...................................................................................................... 70 2.2.2 Serial Wire and JTAG Debug ......................................................................................... 77 2.2.3 Embedded Trace Macrocell (ETM) ................................................................................. 77 2.2.4 Trace Port Interface Unit (TPIU) ..................................................................................... 77 2.2.5 ROM Table ................................................................................................................... 78 2.2.6 Memory Protection Unit (MPU) ....................................................................................... 78 2.2.7 Nested Vectored Interrupt Controller (NVIC) .................................................................... 78 2.2.8 System Timer (SysTick) ................................................................................................. 79 3 Memory Map ........................................................................................................... 82 4 Interrupts ................................................................................................................. 85 5 JTAG Interface ........................................................................................................ 88 5.1 Block Diagram .............................................................................................................. 89 5.2 Signal Description ......................................................................................................... 89 5.3 Functional Description ................................................................................................... 90 5.3.1 JTAG Interface Pins ...................................................................................................... 90 5.3.2 JTAG TAP Controller ..................................................................................................... 92 5.3.3 Shift Registers .............................................................................................................. 92 5.3.4 Operational Considerations ............................................................................................ 93 5.4 Initialization and Configuration ....................................................................................... 95 5.5 Register Descriptions .................................................................................................... 96 3 June 15, 2010 Texas Instruments-Advance Information Stellaris® LM3S9L97 Microcontroller |
同様の部品番号 - LM3S9L97-IQN50-C1 |
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同様の説明 - LM3S9L97-IQN50-C1 |
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