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KS88C2064 データシート(PDF) 5 Page - Samsung semiconductor |
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KS88C2064 データシート(HTML) 5 Page - Samsung semiconductor |
5 / 22 page KS88C2064 PRODUCT OVERVIEW 1-5 PIN DESCRIPTIONS Table 1-1. Pin Descriptions Pin Names Pin Type Pin Description Circuit Type Pin No. Shared Functions P0.0–P0.7 I/O I/O port with nibble-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; also configurable as external interface address lines A8–A15. 3 35–28 A8–A15 P1.0–P1.7 I/O Same general characteristics as port 0; also configurable as external interface address/data lines AD0–AD7. 3 43–36 AD0–AD7 P2.0–P2.3 I/O I/O port with bit-programmable pins; schmitt trigger input or push-pull output and software assignable pull-ups. Lower nibble pins 0–3 are configurable for external interface signals. 5 52–55 AS , DW, DR, DM P2.4–P2.7 I/O P2.4/capture input, interval/PWM output (T0) P2.5/timer 0 clock input (T0CK) P2.6/system clock output (CLO) P2.7/buzzer signal output (BUZ) 6 56–59 T0, T0CK, CLO, BUZ P3.0–P3.7 I/O I/O port with bit-programmable pins; schmitt trigger input or push-pull output and software assignable pull-up; P3.0–P3.7 are alternately used for external interrupt input (noise filters, interrupt enable and pending control); P3.0/timer B clock output (TB)/INT0 P3.1/timer 1/A clock output (TA)/INT1 P3.2/timer 1/A clock input (T1CK)/INT2 4 44–51 TB/INT0, TA/INT1, T1CK/INT2, INT3–INT7 T1CK I/O Timer A external clock input pins. 4 46 P3.2/INT2 TB TA I/O Timer B and 1/A clock output pins. 4 44 45 P3.0/INT0 P3.1/INT1 AS , DW, DR, DM I/O Output pins for external interface control signals. AS : address strobe DW : data memory write DR : data memory read DM : data memory select 5 52–55 P2.0–P2.3 T0 I/O Capture input or interval/PWM output. 6 56 P2.4 T0CK I/O Timer 0 clock input. 6 57 P2.5 |
同様の部品番号 - KS88C2064 |
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同様の説明 - KS88C2064 |
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