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S3C72F5 データシート(PDF) 6 Page - Samsung semiconductor

部品番号 S3C72F5
部品情報  The S3C72F5 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M
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メーカー  SAMSUNG [Samsung semiconductor]
ホームページ  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

S3C72F5 データシート(HTML) 6 Page - Samsung semiconductor

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PRODUCT OVERVIEW
S3C72F5/P72F5
1–6
Table 1–1. S3C72F5 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Number
Share Pin
INT2
I
Quasi-interrupt with detection of rising or
falling edges.
25
P1.2
INT4
I
External interrupt with detection of rising or
falling edges.
26
P1.3
CLO
I/O
Clock output .
27
P2.0
LCDCK
I/O
LCD clock output for display expansion.
28
P2.1
LCDSY
I/O
LCD synchronization clock output for display
expansion.
29
P2.2
TCLO0
I/O
Timer/counter 0 clock output.
30
P3.0
TCLO1
I/O
Timer/counter 1 clock output.
31
P3.1
TCL0
I/O
External clock input for timer/counter 0.
32
P3.2
TCL1
I/O
External clock input for timer/counter 1.
33
P3.3
COM0–COM7
O
LCD common signal output.
34–41
COM8–COM11
I/O
42–45
P4.0–P4.3
COM12–COM15
46–49
P5.0–P5.3
SEG0–SEG39
O
LCD segment signal output.
5–1,
100–66
SEG40–SEG43
I/O
65–62
P9.3–P9.0
SEG44–SEG47
61–58
P8.3–P8.0
SEG48–SEG51
57–54
P7.3–P7.0
SEG52–SEG55
53–50
P6.3/K7–P6.0/K4
K0–K3
I/O
External interrupt. The triggering edge is
selectable.
11–14
P0.0–P0.3
K4–K7
50–53
P6.0–P6.3
VDD
Main power supply.
15
VSS
Ground.
16
RESET
I
Reset signal.
22
VLC1–VLC5
LCD power supply.
10–6
Xin, Xout
Crystal, Ceramic or RC oscillator pins for
system clock.
18, 17
XTin, XTout
Crystal oscillator pins for subsystem clock.
20, 21
TEST
I
Test signal input. (must be connected to VSS)
19
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.


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