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ISLA112P25MREP データシート(PDF) 1 Page - Intersil Corporation

部品番号 ISLA112P25MREP
部品情報  Low Power 12-Bit, 250MSPS ADC
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メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISLA112P25MREP データシート(HTML) 1 Page - Intersil Corporation

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Low Power 12-Bit, 250MSPS ADC
ISLA112P25MREP
The ISLA112P25MREP is a low-power 12-bit, 250MSPS
analog-to-digital converter. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard
CMOS process.
A serial peripheral interface (SPI) port allows for
extensive configurability, as well as fine control of various
parameters such as gain and offset.
Digital output data is presented in selectable LVDS or
CMOS formats. The ISLA112P25MREP is available in a
72 Ld QFN package with an exposed paddle. Operating
from a 1.8V supply, performance is specified over the full
military temperature range (-55°C to +125°C).
Applications
• Power Amplifier Linearization
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
Key Specifications
• SNR = 62.7dBFS for fIN = 105MHz (-1dBFS)
•SFDR = 67dBc for fIN = 105MHz (-1dBFS)
• Total Power Consumption
- 310mW @ 250MSPS (SDR Mode)
- 234mW @ 250MSPS (DDR Mode)
Features
• Programmable Gain, Offset and Skew Control
•1.3GHz Analog Input Bandwidth
• 60fs Clock Jitter
•Over-Range Indicator
• Selectable Clock Divider: ÷1, ÷2 or ÷4
• Clock Phase Selection
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• SDR/DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Built-in Test Patterns
• Single-Supply 1.8V Operation
• Pb-Free (RoHS Compliant)
VID Features
• Specifications per DSCC VID V62/10609
• Full Military Temperature Electrical Performance from
-55°C to +125°C
• Controlled Baseline with One Wafer Fabrication Site
and One Assembly/Test Site
• Full Homogeneous Lot Processing in Wafer Fab
• No Combination of Wafer Fabrication Lots in Assembly
• Full Traceability Through Assembly and Test by
• Date/Trace Code Assignment
• Enhanced Process Change Notification
• Enhanced Obsolescence Management
• Eliminates Need for Up-Screening a COTS Component
Block Diagram
DIGITAL
ERROR
CORRECTION
LVDS/CMOS
DRIVERS
1.25V
CLOCK
GENERATION
SHA
VINP
VINN
12-BIT
250 MSPS
ADC
CLKP
CLKN
SPI
CONTROL
CLKOUTP
CLKOUTN
D[11:0]P
D[11:0]N
ORP
ORN
OUTFMT
OUTMODE
+
VCM
June 25, 2010
FN7646.0


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