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DM74ALS174SJ データシート(PDF) 1 Page - Fairchild Semiconductor |
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DM74ALS174SJ データシート(HTML) 1 Page - Fairchild Semiconductor |
1 / 9 page tm May 2007 ©1986 Fairchild Semiconductor Corporation www.fairchildsemi.com DM74ALS174, DM74ALS175 Rev. 1.2 DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear Features ■ Advanced oxide-isolated ion-implanted Schottky TTL process ■ Pin and functional compatible with LS family counterpart ■ Typical clock frequency maximum is 80MHz ■ Switching performance guaranteed over full temperature and VCC supply range General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchronous clear input, and the quad (DM74ALS175) version features complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output. Ordering Information Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Ordering Code Package Number Package Description DM74ALS174M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow DM74ALS174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow DM74ALS175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide |
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同様の説明 - DM74ALS174SJ |
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