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FM21LD16-60-BGTR データシート(PDF) 7 Page - Ramtron International Corporation |
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FM21LD16-60-BGTR データシート(HTML) 7 Page - Ramtron International Corporation |
7 / 14 page FM21LD16 - 128Kx16 FRAM Rev. 1.0 Dec. 2009 Page 7 of 14 Software Write Protect Timing SRAM Drop-In Replacement The FM21LD16 has been designed to be a drop-in replacement for standard asynchronous SRAMs. The device does not require /CE to toggle for each new address. /CE may remain low indefinitely. While /CE is low, the device automatically detects address changes and a new access is begun. This functionality allows /CE to be grounded as you might with an SRAM. It also allows page mode operation at speeds up to 40MHz. Note that if /CE is tied to ground, the user must be sure /WE is not low at powerup or powerdown events. If /CE and /WE are both low during power cycles, data corruption will occur. Figure 3 shows a pullup resistor on /WE which will keep the pin high during power cycles assuming the MCU/MPU pin tri-states during the reset condition. The pullup resistor value should be chosen to ensure the /WE pin tracks VDD yet a high enough value that the current drawn when /WE is low is not an issue. A 10Kohm resistor draws 330uA when /WE is low and VDD=3.3V. Figure 3. Use of Pullup Resistor on /WE NOTE: If /CE is tied to ground, the user gives up the ability to perform the software write-protect sequence. For applications that require the lowest power consumption, the /CE signal should be active only during memory accesses. The FM21LD16 draws supply current while /CE is low, even if addresses and control signals are static. While /CE is high, the device draws no more than the maximum standby current ISB. The FM21LD16 is backward compatible with the 1Mbit FM20L08 and 256Kbit FM18L08 devices. That is, operating the FM21LD16 with /CE toggling low on every address is perfectly acceptable. In terms of package and pinout, the FM21LD16 is upward compatible with the FM22LD16 (4Mb). The /UB and /LB byte select pins are active for both read and write cycles. They may be used to allow the device to be wired as a 256Kx8 memory. The upper and lower data bytes can be tied together and controlled with the byte selects. Individual byte enables or the next higher address line A(17) may be available from the system processor. Figure 4. FM21LD16 Wired as 256Kx8 CE WE OE A(16:0) DQ FM21LD16 VDD MCU/ MPU R |
同様の部品番号 - FM21LD16-60-BGTR |
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同様の説明 - FM21LD16-60-BGTR |
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