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LC78628E データシート(PDF) 2 Page - Sanyo Semicon Device |
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LC78628E データシート(HTML) 2 Page - Sanyo Semicon Device |
2 / 40 page Continued from preceding page. • Buffers the demodulated EFM signal data in internal RAM and compensates for ±4 frames of jitter due to disc speed fluctuations. • Performs unscrambling and deinterleaving by reordering the demodulated EFM signal data to the stipulated order. • Performs error detection and correction and flag processing (C1: dual errors, C2: dual errors) • The C2 flags are set based on the C1 flags and the result of the C2 processing, and the signal is interpolated or muted according to the C2 flags. Four-sample interpolation is adopted in the interpolation circuit. Linear (average value) interpolation is applied if up to three consecutive errors are indicated by the C2 flags, and muting at the zero level is applied if four or more consecutive errors are indicated. • Performs track jump, focus start, disc motor start/stop, muting on/off, track count, and other operations by executing 8- or 16-bit commands serially input from the system microprocessor. • Supports high-speed disc access operations based on arbitrary track counts. • Provides digital outputs. • Built-in Σ∆ D/A converter based on a third-order noise shaper. • Zero-cross muting • Digital attenuator and deemphasis filter • Support 2 × speed playback • Bilingual function • Built-in text decoder • Five general-purpose I/O ports Features • 80-pin QFP package • Fabricated in a silicon gate CMOS process • 3.3 and 5 V power supply voltages No. 6329-2/40 LC78628E LRSY C2F ROMXA LRCKI BCKI DATAI DOUT GAIN HDCD DFOLO DACKO LRCKO DFORO RWC COIN CQCK SQOUT WRQ CS TEST6 V/P Slice level control Synchronization EFM demodulation CLV digital servo Subcode separation Q CRC Microprocessor interface Servo commander I/O ports Text decoder Crystal oscillator System timing generator 1-bit DAC MUX M U X HDCD decoder Interpolation mute 2k × 8bits RAM C1 and C2 error detection and correction flag processing VCO clock control RAM address generator Bilingual MUX, S–P Digital output 8·Fs HDCD interpolation filter De-emphasis attenuator CLV– CLV+ FSEQ EFMIN DEFI A12795 Block Diagram |
同様の部品番号 - LC78628E |
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同様の説明 - LC78628E |
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