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LC78835 データシート(PDF) 8 Page - Sanyo Semicon Device |
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LC78835 データシート(HTML) 8 Page - Sanyo Semicon Device |
8 / 14 page 2. Initialization Initialization is necessary when power is applied or the system clock is replaced. When the INITB pin has been set to an “L” level, the supply to XIN, BCLK, and LRCK should be connected only after the supply has stabilized at the “L” level. As shown in the figure, a period greater than one LRCK cycle is required. When INITB = “L,” all 18-bit digital filter outputs set to 0, and the D/A converter’s output (CH1OUT, CH2OUT) equals 0 analog output (approximately (VREFH + VREFL)/2 electric potential). 3. System Clock This IC supports four system clock speeds including 384 fs, 392 fs, 448 fs, and 512 fs. These may be selected using the CKSL1 and CKSL2 pins. • CKOUT Pin When operating at 392 fs, clock output is 196 fs or half that of the system clock. All other speeds result in clock output equal to that of the system. No. 4624-8/14 LC78835K, 78835KM CKSL1 CKSL2 System Clock L L 384 fs L H 392 fs H L 448 fs H H 512 fs |
同様の部品番号 - LC78835 |
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同様の説明 - LC78835 |
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