5V19EE901PGGI datasheet(7/35 Pages) IDT

部品番号	5V19EE901PGGI

部品情報	EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

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メーカー	IDT [Integrated Device Technology]

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IDT5V19EE901

EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

CLOCK SYNTHESIZER

IDT® EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

7

IDT5V19EE901

REV K 022310

clocks are at different frequencies, the device will always

remain on the primary clock unless it is absent for two

secondary clock cycles. The secondary clock must always

run at a frequency less than or equal to the primary clock

frequency.

R

eference Divider, Feedback Divider, and

Output Divider

Each PLL incorporates a 7-bit reference divider (D[6:0]) and

a 12-bit feedback divider (N[11:0]) that allows the user to

generate four unique non-integer-related frequencies. Each

output divide supports 8-bit output-divider (PM and Q[7:0]).

The following equation governs how the output frequency is

calculated.

Where FIN is the reference frequency, M is the total

feedback-divider value, D is the reference divider value,

ODIV is the total output-divider value, and FOUT is the

resulting output frequency.

For PLL0,

M = 2 * N + A + 1 (for A>0)

M = 2 * N (for A = 0)

For PLL1, PLL2 and PLL3,

M = N

PM and Q[6:0] are the bits used to program the 8-bit

output-dividers for outputs OUT1-6. OUT0 does not have

any output divide along its path. The 8-bit output-dividers

will bypass or divide down the output banks' frequency with

even integer values ranging from 2 to 256.

There is the option to choose between disabling the

output-divider, utilizing a div/1, a div/2, or the 7-bit Q-divider

by using the PM bit. If the output is disabled, it will be driven

High, Low or High Impedance, depending on OEM[1:0].

Each bank, except for OUT0, has a PM bit. When disabled,

no clocks will appear at the output of the divider, but will

remain powered on. The output divides selection table is

shown below.

Note that the actual 7-bit Q-divider value has a 2 added to

the integer value Q and the outputs are routed through

another div/2 block. The output divider should never be

disabled unless the output bank will never be used during

normal operation. The output frequency range for LVTTL

outputs are from 4.9KHz to 200MHz. The output frequency

for LVPECL/LVDS/HCSL outputs range from 4.9KHz to

500MHz.

Spread Spectrum Generation (PLL0)

PLL0 supports spread spectrum generation capability,

which users have the option of turning on or off. Spread

spectrum profile, frequency, and spread amplitude are fully

programmable. The programmable spread spectrum

generation parameters are TSSC[3:0], NSSC[2:0],

SS_OFFSET[5:0], SD[3:0], DITH, and X2 bits. These bits

are in the memory address from 0xAC to 0xBD for PLL0.

The spread spectrum generation on PLL0 can be

enabled/disabled using the TSSC[3:0] bits. To enable

spread spectrum, set TSSC > '0' and set NSSC[2:0],

SS_OFFSET[5:0], SD[3:0], and the A[3:0] (in the total M

value) accordingly. To disable spread spectrum generation,

set TSSC = '0'.

TSSC[3:0]

These bits are used to determine the number of

phase/frequency detector cycles per spread spectrum cycle

(ssc) steps. The modulation frequency can be calculated

with the TSSC bits in conjunction with the NSSC bits. Valid

TSSC integer values for the modulation frequency range

from 5 to 14. Values of 0 - 4 and 15 should not be used.

NSSC[2:0]

These bits are used to determine the number of

delta-encoded samples used for a single quadrant of the

spread spectrum waveform. All four quadrants of the spread

spectrum waveform are mirror images of each other. The

modulation frequency is also calculated based on the NSSC

bits in conjunction with the TSSC bits. Valid NSSC integer

F

OUT =

M

D

( )

F

IN *

ODIV

(Eq. 1)

Q[6:0]

PM

Output Divider

111 1111

0

Disabled

1/1

<111 1111

0

/2

1

/((Q[6:0] + 2) * 2)

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