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ISL23315UFRUZ-T7A データシート(PDF) 2 Page - Intersil Corporation |
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ISL23315UFRUZ-T7A データシート(HTML) 2 Page - Intersil Corporation |
2 / 20 page ISL23315 2 FN7778.1 August 15, 2011 Block Diagram LEVEL SHIFTER VCC RH GND RL RW SCL SDA A1 A0 POWER-UP INTERFACE, CONTROL AND STATUS LOGIC WR VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY VLOGIC I/O BLOCK Pin Configurations ISL23315 (10 LD MSOP) TOP VIEW ISL23315 (10 LD µTQFN) TOP VIEW 1 2 3 4 5 6 10 9 8 7 SDA VLOGIC A1 A0 GND SCL RL RW RH VCC 9 8 7 6 1 2 3 4 A1 VCC RH GND SCL A0 SDA RW Pin Descriptions MSOP µTQFN SYMBOL DESCRIPTION 110 VLOGIC I2C bus /logic supply. Range 1.2V to 5.5V 2 1 SCL Logic Pin - Serial bus clock input 3 2 SDA Logic Pin - Serial bus data input/open drain output 4 3 A0 Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND 5 4 A1 Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND 6 5 RL DCP “low” terminal 7 6 RW DCP wiper terminal 8 7 RH DCP “high” terminal 98 VCC Analog power supply. Range 1.7V to 5.5V 10 9 GND Ground pin |
同様の部品番号 - ISL23315UFRUZ-T7A |
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同様の説明 - ISL23315UFRUZ-T7A |
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