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FM21LD16 データシート(PDF) 3 Page - Ramtron International Corporation |
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FM21LD16 データシート(HTML) 3 Page - Ramtron International Corporation |
3 / 15 page FM21LD16 - 128Kx16 FRAM Rev. 1.1 Apr. 2011 Page 3 of 15 Functional Truth Table 1,2 /CE /WE A(16:2) A(1:0) Operation H X X X Standby/Idle ↓ H V V Read L H No Change Change Page Mode Read L H Change V Random Read ↓ L V V /CE-Controlled Write L ↓ V V /WE-Controlled Write 2 L ↓ No Change V Page Mode Write 3 ↑ X X X Starts Precharge Notes: 1) H=Logic High, L=Logic Low, V=Valid Data, X=Don’t Care. 2) /WE-controlled write cycle begins as a Read cycle and A(16:2) is latched then. 3) Addresses A(1:0) must remain stable for at least 10 ns during page mode operation. 4) For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first. Byte Select Truth Table /WE /OE /LB /UB Operation H H X X Read; Outputs Disabled X H H H L H L Read upper byte; Hi-Z lower byte L H Read lower byte; Hi-Z upper byte L L Read both bytes L X H L Write upper byte; Mask lower byte L H Write lower byte; Mask upper byte L L Write both bytes The /UB and /LB pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 256Kx8. |
同様の部品番号 - FM21LD16 |
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同様の説明 - FM21LD16 |
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