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FM21LD16-60-BG データシート(PDF) 8 Page - Ramtron International Corporation

部品番号 FM21LD16-60-BG
部品情報  2Mbit F-RAM Memory
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メーカー  RAMTRON [Ramtron International Corporation]
ホームページ  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM21LD16-60-BG データシート(HTML) 8 Page - Ramtron International Corporation

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FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011
Page 8 of 15
SRAM Drop-In Replacement
The FM21LD16 has been designed to be a drop-in
replacement for standard asynchronous SRAMs. The
device does not require /CE to toggle for each new
address. /CE may remain low for as long as 10µs.
While /CE is low, the device automatically detects
address changes and a new access is begun. It also
allows page mode operation at speeds up to 33MHz.
The user must be sure /CE is not low at powerup
or powerdown events. If /CE and /WE are both
low during power cycles, data corruption will
occur. Figure 6 shows a pullup resistor on /CE
which will keep the pin high during power cycles
assuming the MCU/MPU pin is tri-stated during
the system reset. The pullup resistor value should
be chosen to ensure the /CE pin tracks VDD yet a
high enough value that the current drawn when
/CE is low is not an issue. A 10K ohm resistor
draws 330µA when /CE is low and VDD=3.3V.
Figure 5. Use of Pullup Resistor on /WE
For applications that require the lowest power
consumption, the /CE signal should be active only
during memory accesses.
The FM21LD16 draws
supply current while /CE is low, even if addresses and
control signals are static. While /CE is high, the
device draws no more than the maximum standby
current ISB.
The FM21LD16 is backward compatible with the
1Mbit FM20L08 and 256Kbit FM18L08 devices.
That is, operating the FM21LD16 with /CE toggling
low on every address is perfectly acceptable. In terms
of package and pinout, the FM21LD16 is upward
compatible with the FM22LD16 (4Mb).
The /UB and /LB byte select pins are active for both
read and write cycles. They may be used to allow the
device to be wired as a 256Kx8 memory. The upper
and lower data bytes can be tied together and
controlled with the byte selects. Individual byte
enables or the next higher address line A(17) may be
available from the system processor.
Figure 6. FM21LD16 Wired as 256Kx8
CE
WE
OE
A(16:0)
DQ
FM21LD16
VDD
MCU/
MPU
R


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