データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

FM21LD16-60-BGTR データシート(PDF) 5 Page - Ramtron International Corporation

部品番号 FM21LD16-60-BGTR
部品情報  2Mbit F-RAM Memory
Download  15 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  RAMTRON [Ramtron International Corporation]
ホームページ  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM21LD16-60-BGTR データシート(HTML) 5 Page - Ramtron International Corporation

  FM21LD16-60-BGTR Datasheet HTML 1Page - Ramtron International Corporation FM21LD16-60-BGTR Datasheet HTML 2Page - Ramtron International Corporation FM21LD16-60-BGTR Datasheet HTML 3Page - Ramtron International Corporation FM21LD16-60-BGTR Datasheet HTML 4Page - Ramtron International Corporation FM21LD16-60-BGTR Datasheet HTML 5Page - Ramtron International Corporation FM21LD16-60-BGTR Datasheet HTML 6Page - Ramtron International Corporation FM21LD16-60-BGTR Datasheet HTML 7Page - Ramtron International Corporation FM21LD16-60-BGTR Datasheet HTML 8Page - Ramtron International Corporation FM21LD16-60-BGTR Datasheet HTML 9Page - Ramtron International Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 15 page
background image
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011
Page 5 of 15
along with a new column address provides a page
mode write access.
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is being prepared for a
new access. Precharge is user-initiated by driving the
/CE signal high. It must remain high for at least the
minimum precharge time tPC.
Precharge is also activated by changing the upper
addess A(16:2). The current row is first closed prior
to accessing the new row. The device automatically
detects an upper order address change which starts a
precharge operation, the new address is latched, and
the new read data is valid within the tAA address
access time. Refer to the Read Cycle Timing 1
diagram on page 10. Likewise a similar sequence
occurs for write cycles. Refer to the Write Cycle
Timing 3 diagram on page 12.
The rate at which
random addresses can be issued is tRC and tWC,
respectively.
Software Write Protection
The 128Kx16 address space is divided into 8 sectors
(blocks) of 16Kx16 each. Each sector can be
individually software write-protected and the settings
are nonvolatile. A unique address and command
sequence invokes the write protection mode.
To modify write protection, the system host must
issue six read commands, three write commands, and
a final read command. The specific sequence of read
addresses must be provided in order to access to the
write protect mode. Following the read address
sequence, the host must write a data byte that
specifies the desired protection state of each sector.
For confirmation, the system must then write the
complement of the protection byte immediately
following the protection byte. Any error that occurs
including read addresses in the wrong order, issuing a
seventh read address, or failing to complement the
protection value will leave the write protection
unchanged.
The write protect state machine monitors all
addresses, taking no action until this particular
read/write sequence occurs. During the address
sequence, each read will occur as a valid operation
and data from the corresponding addresses will be
driven onto the data bus. Any address that occurs out
of sequence will cause the software protection state
machine to start over. After the address sequence is
completed, the next operation must be a write cycle.
The data byte contains the write-protect settings. This
value will not be written to the memory array, so the
address is a don’t-care. Rather it will be held pending
the next cycle, which must be a write of the data
complement to the protection settings. If the
complement is correct, the write protect settings will
be adjusted. If not, the process is aborted and the
address sequence starts over. The data value written
after the correct six addresses will not be entered into
memory.
The protection data byte consists of 8-bits, each
associated with the write protect state of a sector. The
data byte must be driven to the lower 8-bits of the
data bus, DQ(7:0). Setting a bit to 1 write protects the
corresponding sector; a 0 enables writes for that
sector. The following table shows the write-protect
sectors with the corresponding bit that controls the
write-protect setting.
Write Protect Sectors – 16K x16 blocks
Sector 7
1FFFFh – 1C000h
Sector 6
1BFFFh – 18000h
Sector 5
17FFFh – 14000h
Sector 4
13FFFh – 10000h
Sector 3
0FFFFh – 0C000h
Sector 2
0BFFFh – 08000h
Sector 1
07FFFh – 04000h
Sector 0
03FFFh – 00000h
The write-protect read address sequence follows:
1.
12555h *
2.
1DAAAh
3.
01333h
4.
0ECCCh
5.
000FFh
6.
1FF00h
7.
1DAAAh
8.
0ECCCh
9.
0FF00h
10.
00000h
* If /CE is low entering the sequence, then an
address of 00000h must precede 12555h.
The address sequence provides a very secure way of
modifying the protection. The write-protect sequence
has a 1 in 3 x 1032 chance of randomly accessing
exactly the 1st six addresses. The odds are further
reduced by requiring three more write cycles, one that
requires an exact inversion of the data byte. A flow
chart of the entire write protect operation is shown in
Figure 2. The write-protect settings are nonvolatile.
The factory default: all blocks are unprotected.


同様の部品番号 - FM21LD16-60-BGTR

メーカー部品番号データシート部品情報
logo
Ramtron International C...
FM21LD16-60-BGTR RAMTRON-FM21LD16-60-BGTR Datasheet
217Kb / 14P
   2Mbit F-RAM Memory
logo
Cypress Semiconductor
FM21LD16-60-BGTR CYPRESS-FM21LD16-60-BGTR Datasheet
438Kb / 15P
   2Mbit F-RAM Memory
More results

同様の説明 - FM21LD16-60-BGTR

メーカー部品番号データシート部品情報
logo
Ramtron International C...
FM21LD16 RAMTRON-FM21LD16 Datasheet
217Kb / 14P
   2Mbit F-RAM Memory
FM21L16 RAMTRON-FM21L16_11 Datasheet
292Kb / 15P
   2Mbit F-RAM Memory
logo
Cypress Semiconductor
FM21LD16 CYPRESS-FM21LD16 Datasheet
438Kb / 15P
   2Mbit F-RAM Memory
FM28V202 CYPRESS-FM28V202 Datasheet
479Kb / 18P
   2Mbit (128Kx16)F-RAM Memory
logo
Ramtron International C...
FM22LD16 RAMTRON-FM22LD16_09 Datasheet
215Kb / 14P
   4Mbit F-RAM Memory
logo
Cypress Semiconductor
FM22LD16 CYPRESS-FM22LD16 Datasheet
434Kb / 14P
   4Mbit F-RAM Memory
FM22LD16 CYPRESS-FM22LD16_13 Datasheet
424Kb / 15P
   4Mbit F-RAM Memory
logo
Ramtron International C...
FM21L16 RAMTRON-FM21L16 Datasheet
224Kb / 14P
   2Mbit FRAM Memory
FM22LD16 RAMTRON-FM22LD16 Datasheet
211Kb / 14P
   4Mbit F-RAM Memory
logo
Cypress Semiconductor
FM23MLD16 CYPRESS-FM23MLD16 Datasheet
220Kb / 13P
   8Mbit F-RAM Memory
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com