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FM21LD16-60-BGTR データシート(PDF) 2 Page - Ramtron International Corporation

部品番号 FM21LD16-60-BGTR
部品情報  2Mbit F-RAM Memory
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メーカー  RAMTRON [Ramtron International Corporation]
ホームページ  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM21LD16-60-BGTR データシート(HTML) 2 Page - Ramtron International Corporation

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FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011
Page 2 of 15
Figure 1. Block Diagram
Pin Description
Pin Name
Type
Pin Description
A(16:0)
Input
Address inputs: The 17 address lines select one of 131,072 words in the F-RAM array. The
lowest two address lines A(1:0) may be used for page mode read and write operations.
/CE
Input
Chip Enable input: The device is selected and a new memory access begins when /CE is
low. The entire address is latched internally on the falling edge of /CE. Subsequent changes
to the A(1:0) address inputs allow page mode operation when /CE is low.
/WE
Input
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM21LD16 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE
latches a new column address for page mode write cycles.
/OE
Input
Output Enable: When /OE is low, the FM21LD16 drives the data bus when valid read data is
available. Deasserting /OE high tri-states the DQ pins.
DQ(15:0)
I/O
Data: 16-bit bi-directional data bus for accessing the F-RAM array.
/UB
Input
Upper Byte Select: Enables DQ(15:8) pins during reads and writes. Deasserting /UB high
tri-states the DQ pins. If the user does not perform byte writes and the device is not
configured as a 256Kx8, the /UB and /LB pins may be tied to ground.
/LB
Input
Lower Byte Select: Enables DQ(7:0) pins during reads and writes. Deasserting /LB high tri-
states the DQ pins. If the user does not perform byte writes and the device is not configured
as a 256Kx8, the /UB and /LB pins may be tied to ground.
VDD
Supply
Supply Voltage
VSS
Supply
Ground


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