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FM24C04B-GTR データシート(PDF) 3 Page - Ramtron International Corporation |
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FM24C04B-GTR データシート(HTML) 3 Page - Ramtron International Corporation |
3 / 12 page FM24C04B Rev. 1.3 Feb. 2011 Page 3 of 12 Overview The FM24C04B is a serial FRAM memory. The memory array is logically organized as 512 x 8 and is accessed using an industry standard two-wire interface. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM24C04B and a serial EEPROM with the same pinout relates to its superior write performance. Memory Architecture When accessing the FM24C04B, the user addresses 512 locations each with 8 data bits. These data bits are shifted serially. The 512 addresses are accessed using the two-wire protocol, which includes a slave address (to distinguish other devices), a page address, and a word address. The word address consists of 8- bits that specify one of 256 addresses. The page address is 1-bit and so there are 2 pages of 256 locations. The complete address of 9-bits specifies each byte address uniquely. Most functions of the FM24C04B either are controlled by the two-wire interface or are handled automatically by on-board circuitry. The memory is read or written at the speed of the two-wire bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section below. Users can expect several obvious system benefits from the FM24C04B due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM24C04B contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that VDD is within data sheet tolerances to prevent incorrect operation. Two-wire Interface The FM24C04B employs a bi-directional two-wire bus protocol using few pins and little board space. Figure 2 illustrates a typical system configuration using the FM24C04B in a microcontroller-based system. The industry standard two-wire bus is familiar to many users but is described in this section. By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM24C04B is always a slave device. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions: Start, Stop, Data bit, and Acknowledge. Figure 3 illustrates the signal conditions that specify the four states. Detailed timing diagrams are shown in the electrical specifications. Microcontroller SDA SCL FM24C04B A1 A2 SDA SCL FM24C04B A1 A2 VDD Rmin = 1.8 Kohm Rmax = tR/Cbus VDD Figure 2. Typical System Configuration |
同様の部品番号 - FM24C04B-GTR |
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同様の説明 - FM24C04B-GTR |
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