データシートサーチシステム |
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FM24C04C-G データシート(PDF) 7 Page - Ramtron International Corporation |
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FM24C04C-G データシート(HTML) 7 Page - Ramtron International Corporation |
7 / 12 page FM24C04C Rev. 1.1 June 2011 Page 7 of 12 S A Slave Address 1 Data Byte 1 P By Master By F-RAM Start Address Stop Acknowledge No Acknowledge Data Figure 7. Current Address Read S A Slave Address 1 Data Byte 1 P By Master By F-RAM Start Address Stop Acknowledge No Acknowledge Data Data Byte A Acknowledge Figure 8. Sequential Read S A Slave Address 1 Data Byte 1 P By Master By F-RAM Start Address Stop No Acknowledge Data Data Byte A Acknowledge S A Slave Address 0 Word Address A Start Address Acknowledge Figure 9. Selective (Random) Read Endurance The FM24C04C internally operates with a read and restore mechanism. Therefore, endurance cycles are applied for each read or write cycle. The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM24C04C, a row is 64 bits wide. Every 8-byte boundary marks the beginning of a new row. Endurance can be optimized by ensuring frequently accessed data is located in different rows. Regardless, F-RAM read and write endurance is effectively unlimited at the 1MHz two-wire speed. Even at 3000 accesses per second to the same row, 10 years time will elapse before 1 trillion endurance cycles occur. |
同様の部品番号 - FM24C04C-G |
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同様の説明 - FM24C04C-G |
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