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FM24C64B-G データシート(PDF) 6 Page - Ramtron International Corporation

部品番号 FM24C64B-G
部品情報  64Kb Serial 5V F-RAM Memory
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メーカー  RAMTRON [Ramtron International Corporation]
ホームページ  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM24C64B-G データシート(HTML) 6 Page - Ramtron International Corporation

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FM24C64B
Rev. 1.3
Feb. 2011
6 of 12
S
A
Slave Address
0
Address MSB
A
Data Byte
A
P
By Master
By FM24C64B
Start
Address & Data
Stop
Acknowledge
Address LSB
A
Figure 5. Byte Write
S
A
Slave Address
0
Address MSB
A
Data Byte
A
P
By Master
By FM24C64B
Start
Address & Data
Stop
Acknowledge
Address LSB
A
Data Byte
A
Figure 6. Multiple-Byte Write
Read Operation
There are two basic types of read operations. They
are current address read and selective address read. In
a current address read, the FM24C64B uses the
internal address latch to supply the address. In a
selective read, the user performs a procedure to set
the address to a specific value.
Current Address & Sequential Read
The FM24C64B uses an internal latch to supply the
address for a read operation. A current address read
uses the existing value in the address latch as a
starting place for the read operation. The system
reads from the address immediately following that of
the last operation.
To perform a current address read, the bus master
supplies a device address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving
the
complete
device
address,
the
FM24C64B will begin shifting out data from the
current address on the next clock. The current address
is the value held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
Each time the bus master acknowledges a byte, this
indicates that the FM24C64B should read out the
next sequential byte.
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
likely create a bus contention as the FM24C64B
attempts to read out additional data onto the bus. The
four valid methods are:
1. The bus master issues a no-acknowledge in the
9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in Figures 7-9. This is the
preferred method.
2. The bus master issues a no-acknowledge in the
9th clock cycle and a start in the 10th.
3. The bus master issues a stop in the 9th clock
cycle.
4. The bus master issues a start in the 9th clock
cycle.
If the internal address reaches 1FFFh, it will wrap
around to 0000h on the next read cycle. Figures 7 and
8 show the proper operation for current address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
To perform a selective read, the bus master sends out
the device address with the LSB set to 0. This
specifies a write operation. According to the write
protocol, the bus master then sends the address bytes
that are loaded into the internal address latch. After
the FM24C64B acknowledges the address, the bus


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