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FM1808B-SG データシート(PDF) 4 Page - Ramtron International Corporation |
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FM1808B-SG データシート(HTML) 4 Page - Ramtron International Corporation |
4 / 11 page FM1808B – 256Kb Bytewide 5V F-RAM Rev. 1.2 Mar. 2011 Page 4 of 11 Precharge Operation The precharge operation is an internal condition that prepares the memory for a new access. All memory cycles consist of a memory access and a precharge. The precharge is initiated by deasserting the /CE pin high. It must remain high for at least the minimum precharge time tPC. The user determines the beginning of this operation since a precharge will not begin until /CE rises. However, the device has a maximum /CE low time specification that must be satisfied. Endurance Internally, a F-RAM operates with a read and restore mechanism. Therefore, each read and write cycle involves a change of state. The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM1808B, a row is 64 bits wide. Every 8-byte boundary marks the beginning of a new row. Endurance can be optimized by ensuring frequently accessed data is located in different rows. Regardless, F-RAM offers substantially higher write endurance than other nonvolatile memories. The rated endurance limit of 10 12 cycles will allow 3,000 accesses per second to the same row for over 10 years. F-RAM Design Considerations When designing with F-RAM for the first time, users of SRAM will recognize a few minor differences. First, bytewide F-RAM memories latch each address on the falling edge of chip enable. This allows the address bus to change after starting the memory access. Since every access latches the memory address on the falling edge of /CE, users cannot ground it as they might with SRAM. Users who are modifying existing designs to use F- RAM should examine the memory controller for timing compatibility of address and control pins. Each memory access must be qualified with a low transition of /CE. In many cases, this is the only change required. An example of the signal relationships is shown in Figure 2 below. Also shown is a common SRAM signal relationship that will not work for the FM1808B. The reason for /CE to strobe for each address is two- fold: it latches the new address and creates the necessary precharge period while /CE is high. Valid Strobing of /CE FRAM Signaling CE Address A1 A2 Data D1 D2 Invalid Strobing of /CE SRAM Signaling CE Address A1 A2 Data D1 D2 Figure 2. Chip Enable and Memory Address Relationships |
同様の部品番号 - FM1808B-SG |
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同様の説明 - FM1808B-SG |
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