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LB11870 データシート(PDF) 9 Page - Sanyo Semicon Device |
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LB11870 データシート(HTML) 9 Page - Sanyo Semicon Device |
9 / 14 page LB11870 No.7256-9/14 Continued from preceding page. Pin No. Symbol Pin Description Equivalent Circuit 25 FGFIL FG filter connection. If noise on the FG signal input is a problem, insert a capacitor (up to about 2200pF) between this pin and ground. 26 CSD Sets the rotor constraint protection circuit operating time and the initial reset pulse. A protection operating time of about 8 seconds can be set by insert a capacitor of about 0.068 μF between this pin and ground. If the rotor constraint protection circuit is not used, insert a resistor and a capacitor in parallel between this pin and ground. (Values: about 220k Ω and 4700pF) 27 CLD Sets the phase lock state signal mask time. A mask time of about 90ms can be set by inserting a capacitor of about 0.1 μF between this pin and ground. Leave this pin open if masking is not required. 28 FGS FG Schmitt output. 29 LD Phase lock state detection output. This output goes to the on state (low level) when the phase is locked. Continued on next page. 25 VREG VREG 300 Ω 26 VREG 27 300 Ω VREG 28 VREG 29 |
同様の部品番号 - LB11870_07 |
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同様の説明 - LB11870_07 |
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