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74FCT388915T70PY データシート(PDF) 9 Page - Integrated Device Technology

部品番号 74FCT388915T70PY
部品情報  3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
Logo IDT - Integrated Device Technology

74FCT388915T70PY データシート(HTML) 9 Page - Integrated Device Technology

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COMMERCIALTEMPERATURERANGE
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
9
t
S YNC IN PUT
t
"Q" OUTPUTS
t
tt
t
tPD
SYNC IN PUT
(SYNC (1) or
SYNC (0))
FEED BAC K
INPUT
Q/2 OUTPUT
Q0-Q4
OUTPUTS
Q5 OUTPUT
2Q OUTPUT
t
SKEW f
SKEW r
SKEW f
S KEW ALL
S KEW r
CYCLE
CYCLE
1.5V
VCC/2
VCC/2
VCC/2
VCC/2
V CC/2
CONTROL
INPUT
3V
1.5V
0V
3V
0V
OUTP UT
NORM ALLY
LOW
OUTP UT
NORM ALLY
HIGH
SW ITCH
6V
SW ITCH
GND
VOL
0.3V
0.3V
tPLZ
tPZL
tPZH
tPHZ
3V
0V
1.5V
1.5V
ENA BLE
D ISAB LE
VOH
Pulse
Generator
D.U.T.
V CC
V IN
V OUT
100
Ω
100
Ω
RT
V CC
20pF
CL
Pulse
Generator
D.U.T.
V CC
V IN
V OUT
500
Ω
GND
6.0V
500
Ω
RT
(These waveforms represent the configuration of Figure 3a)
NOTES:
1. The FCT388915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation around a center point.
3. If a Q ouput is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q output would run at twice
the SYNC frequency and the Q/2 output would run at half the SYNC frequency.
Propagation Delay, Output Skew
TEST CIRCUITS AND WAVEFORMS
Test
Switch
Disable Low
6V
Enable Low
Disable High
GND
Enable High
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: tF
≤ 2.5ns; tR ≤ 2.5ns.
Enable and Disable Times
Enable and Disable Test Circuit
50
Ω
Ω
Ω
Ω
Ω to VCC/2, CL = 20pF


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