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STEF05PUR データシート(PDF) 10 Page - STMicroelectronics |
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STEF05PUR データシート(HTML) 10 Page - STMicroelectronics |
10 / 20 page Typical application STEF05 10/20 Doc ID 019055 Rev 4 The addition of an external Cdv/dt also influences the initial delay time, defined as the time between the Enable signal going high and the start of the VOUT slope (Figure 5). The contribution of the external capacitor to this time interval can be estimated by using the following theoretical formula: Equation 3 Figure 5. Delay time and VOUT ramp-up time 5.4 Enable/Fault pin The Enable/Fault pin has the dual function of controlling the output of the device and, at the same time, of providing information about the device status to the application. When it is used as a standard Enable pin, it should be connected to an external open-drain or open-collector device. In this case, when it is pulled at low logic level, it turns the output of the E-Fuse off. If this pin is left floating, since it has internal pull-up circuitry, the output of the E-Fuse is kept ON in normal operating conditions. In case of thermal fault, the pin is pulled to an intermediate state ( Figure 6). This signal can be provided to a monitor circuit, informing it that a thermal shutdown has occurred, or it can be directly connected to the Enable/Fault pins of other STEFxx devices on the same application in order to achieve a simultaneous enable/disable feature. When a thermal fault occurs, the device can be reset either by cycling the supply voltage or by pulling down the Enable pin below the Vil threshold and then releasing it. delay time 500 10 6 – 13.6 106 × + × C dvdt × = AM09870v1 0 1 2 3 4 5 6 Time EN/Fault VOUT delay time ramp-up time |
同様の部品番号 - STEF05PUR |
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同様の説明 - STEF05PUR |
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