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ADMP441ACEZ-RL7 データシート(PDF) 4 Page - Analog Devices |
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ADMP441ACEZ-RL7 データシート(HTML) 4 Page - Analog Devices |
4 / 16 page ADMP441 Data Sheet Rev. A | Page 4 of 16 I²S DIGITAL INPUT/OUTPUT –40°C < TA < +85°C, 1.8 V < VDD < 3.3 V, unless otherwise noted. Table 2. Limit1 Parameter Symbol Test Conditions/Comments Min Max Unit DIGITAL INPUT Voltage Input Low (L/R, WS, SCK) VIL 0 0.25 × VDD V Voltage Input High (L/R, WS, SCK) VIH 0.7 × VDD VDD V SD DIGITAL OUTPUT Voltage Output Low VOL VDD = 1.8 V, ISINK = 0.25 mA 0.1 × VDD V Voltage Output Low VOL VDD = 1.8 V, ISINK = 0.7 mA 0.3 × VDD V Voltage Output High VOH VDD = 1.8 V, ISINK = 0.7 mA 0.7 × VDD V Voltage Output High VOH VDD = 1.8 V, ISINK = 0.25 mA 0.9 × VDD V Voltage Output Low VOL VDD = 3.3 V, ISINK = 0.5 mA 0.1 × VDD V Voltage Output Low VOL VDD = 3.3 V, ISINK = 1.7 mA 0.3 × VDD V Voltage Output High VOH VDD = 3.3 V, ISINK = 1.7 mA 0.7 × VDD V Voltage Output High VOH VDD = 3.3 V, ISINK = 0.5 mA 0.9 × VDD V 1 Limits based on characterization results; not production tested. Table 3. Serial Data Port Timing Specifications Parameter Description Min Max Unit tSCH SCK high 50 ns tSCL SCK low 50 ns tSCP SCK period 312 ns fSCK SCK frequency 0.5 3.2 MHz tWSS WS setup 0 ns tWSH WS hold 20 ns fWS WS frequency 7.8 49.3 kHz TIMING DIAGRAM SCK WS SD tSCP tSCH tSCL tWSH tWSS Figure 3. Serial Data Port Timing |
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