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SL74LV374 データシート(PDF) 4 Page - System Logic Semiconductor |
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SL74LV374 データシート(HTML) 4 Page - System Logic Semiconductor |
4 / 8 page SL74LV374 System Logic Semiconductor SLS AC CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns) Test VCC, Limits Symbol Parameter conditions V 25 °C -40 °C to 85 °C 125 °C Unit min max min max min max tPHL, tPLH from CP to Qn Propagation delay Figure 1 1.2 2.0 3.0 - - - 180 45 27 - - - 230 56 34 - - - 270 68 41 ns tPHZ tPLZ from OE to Qn Propagation delay Figure 3 1.2 2.0 3.0 - - - 160 38 25 - - - 200 57 36 - - - 240 68 43 tPZH tPZL from OE to Qn Propagation delay Figure 3 1.2 2.0 3.0 - - - 160 38 23 - - - 200 48 29 - - - 240 58 35 tTHL, tTLH HIGH-to-LOW and LOW-to- HIGH transition time Figure 1 1.2 2.0 3.0 - - - 75 16 10 - - - 100 20 13 - - - 120 24 15 tW Clock pulse width HIGH or LOW Figure 1 1.2 2.0 3.0 250 18 11 - - - 350 23 14 - - - 540 28 17 - - - tSU Set-up time Dn to CP Figure 2 1.2 2.0 3.0 45 13 8 - - - 50 17 10 - - - 100 20 12 - - - tH Hold time Dn to CP Figure 2 1.2 2.0 3.0 25 5 5 - - - 25 5 5 - - - 25 5 5 - - - fc CP naximum pulse frequency Figure 1 2.0 3.0 - - 27 46 - - 22 37 - - 18 31 MHz CI Input capacitance 3.0 - 7 - - - - pF CPD Power dissipation capacitance (per flip-flop) VI = 0 V or VCC 3.0 - 34 - - - - |
同様の部品番号 - SL74LV374 |
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同様の説明 - SL74LV374 |
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