 |
データシートサーチシステム |
|
|
データシートサーチシステム |
|
SM34020A データシート(PDF) 7 Page - Texas Instruments |
|
||||||||||||||||||||||||||||||
SM34020A データシート(HTML) 7 Page - Texas Instruments |
|
|
7 / 94 page  SM34020A GRAPHICS SYSTEM PROCESSOR SGUS057 − FEBRUARY 2005 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) TERMINAL DESCRIPTION NAME TYPE † DESCRIPTION VIDEO INTERFACE (CONTINUED) HSYNC I/O Horizontal sync. HSYNC is the horizontal sync signal that controls external video circuitry. HSYNC can be programmed to be either an input or an output by modifying a control bit in the DPYCTL register. As an output, HSYNC is the active-low horizontal-sync signal generated by the SM34020A on-chip video timers. As an input, HSYNC synchronizes the SM34020A video-control registers to externally generated horizontal-sync pulses. The actual synchronization can be programmed to begin at any VCLK cycle; this allows for any external pipelining of signals. Immediately following reset, HSYNC is configured as an input. SCLK I Serial data clock. SCLK is the same as the signal that drives VRAM serial data registers. SCLK allows the SM34020A to track the VRAM serial-data-register count, providing serial-register transfer and midline-reload cycles. (SCLK can be asynchronous to VCLK; however, it typically has a frequency that is a multiple of the VCLK frequency). VCLK I Video clock. VCLK is derived from a multiple of the video system’s dot clock and is used internally to drive the video timing logic. VSYNC I/O Vertical sync. VSYNC is the vertical sync signal that controls external video circuitry. VSYNC can be programmed to be either an input or an output by modifying a control bit in the DPYCTL register. As an output, VSYNC is the active-low vertical-sync signal generated by the SM34020A on-chip video timers. As an input, VSYNC synchronizes the SM34020A video-control registers to externally generated vertical-sync pulses. The actual synchronization can be programmed to begin at any horizontal line; this allows for any external pipelining of signals. Immediately following reset, VSYNC is configured as an input. † I = input, O = output ‡ For proper SM34020A operation, all VCC and VSS pins must be connected externally. Not Recommended for New Designs |
同様の部品番号 - SM34020A |
|
同様の説明 - SM34020A |
|
|
リンク URL |
| プライバシーポリシー |
| ALLDATASHEET.JP |
| ALLDATASHEETはお客様のビジネスに役立ちますか？ [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
