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SM320C32PCMM50EP データシート(PDF) 5 Page - Texas Instruments |
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SM320C32PCMM50EP データシート(HTML) 5 Page - Texas Instruments |
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5 / 44 page  SM320C32EP DIGITAL SIGNAL PROCESSOR SGUS038 − AUGUST 2002 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 pin functions This section provides signal descriptions for the SM320C32-EP device. The following table lists each signal (grouped by function), the number of pins, operating modes, and a brief signal description. Pin Functions PIN TYPE† DESCRIPTION CONDITIONS WHEN NAME NO. TYPE† DESCRIPTION WHEN SIGNAL IS IN HIGH Z‡ EXTERNAL BUS INTERFACE (70 PINS) D31 − D0 32 I/O/Z 32-bit data port of the external bus interface S H R A23 − A0 24 O/Z 24-bit address port of the external bus interface S H R R/W 1 O/Z Read / write for external memory interface. R / W is high when a read is performed and low when a write is performed over the parallel interface. S H R IOSTRB 1 O/Z External peripheral I / O strobe for the external memory interface S H STRB0_B3 /A −1 1 O/Z External memory-access strobe 0, byte enable 3 for 32-bit external memory interface and address pin for 8-bit and 16-bit external memory interface S H STRB0_B2 /A −2 1 O/Z External memory-access strobe 0, byte enable 2 for 32-bit external memory interface and address pin for 8-bit external memory interface S H STRB0_B1 1 O/Z External memory-access strobe 0, byte enable 1 for the external memory interface S H STRB0_B0 1 O/Z External memory-access strobe 0, byte enable 0 for the external memory interface S H STRB1_B3 /A −1 1 O/Z External memory-access strobe 1, byte enable 3 for 32-bit external memory interface and address pin for 8-bit and 16-bit external memory interface S H STRB1_B2 /A −2 1 O/Z External memory-access strobe 1, byte enable 2 for 32-bit external memory interface and address pin for 8-bit external memory interface S H STRB1_B1 1 O/Z External memory-access strobe 1, byte enable 1 for the external memory interface S H STRB1_B0 1 O/Z External memory-access strobe 1, byte enable 0 for the external memory interface S H RDY 1 I Ready. RDY indicates that the external device is prepared for an external memory interface transaction to complete. HOLD 1 I Hold signal for external memory interface. When HOLD is a logic low, any ongoing transaction is completed. A23 − A0, D31 − D0, IOSTRB, STRB0_Bx, STRB1_Bx, and R / W are placed in the high-impedance state, and all transactions over the external memory interface are held until HOLD becomes a logic high or the NOHOLD bit of the STRB0 bus-control register is set. HOLDA 1 O/Z Hold acknowledge for external memory interface. HOLDA is generated in response to a logic low on HOLD. HOLDA indicates that A23 − A0, D31 − D0, IOSTRB, STRB0_Bx, STRB1_Bx, and R / W are in the high-impedance state and that all transactions over the memory are held. HOLDA is high in response to a logic high of HOLD or when the NOHOLD bit of the external bus-control register is set. S PRGW 1 I Program memory width select. When PRGW is a logic low, program is fetched as a single 32-bit word. When PRGW is a logic high, two 16-bit program fetches are performed to fetch a single 32-bit instruction word. The status of PRGW at device reset affects the reset value of the STRB0 and STRB1 bus-control register. † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling capacitor is 0.1 µF. |
同様の部品番号 - SM320C32PCMM50EP |
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同様の説明 - SM320C32PCMM50EP |
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