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SM320VC5416-EP データシート(PDF) 9 Page - Texas Instruments

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部品番号 SM320VC5416-EP
部品情報  SM320VC5416-EP Fixed-Point Digital Signal Processor
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

SM320VC5416-EP データシート(HTML) 9 Page - Texas Instruments

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Features
1
July 2003
SGUS048
1
SM320VC5416-EP Features
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D 40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
D 17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
D Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
D Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D Data Bus With a Bus Holder Feature
D Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
D 128K x 16-Bit On-Chip RAM Composed of:
− Eight Blocks of 8K
× 16-Bit On-Chip
Dual-Access Program/Data RAM
− Eight Blocks of 8K
× 16-Bit On-Chip
Single-Access Program RAM
D 16K × 16-Bit On-Chip ROM Configured for
Program Memory
D Enhanced External Parallel Interface (XIO2)
D Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
D Block-Memory-Move Instructions for Better
Program and Data Management
D Instructions With a 32-Bit Long Word
Operand
D Instructions With Two- or Three-Operand
Reads
D Arithmetic Instructions With Parallel Store
and Parallel Load
D Conditional Store Instructions
D Fast Return From Interrupt
D On-Chip Peripherals
− Software-Programmable Wait-State
Generator and Programmable
Bank-Switching
− On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With
External Clock Source
− One 16-Bit Timer
− Six-Channel Direct Memory Access
(DMA) Controller
− Three Multichannel Buffered Serial Ports
(McBSPs)
− 8/16-Bit Enhanced Parallel Host-Port
Interface (HPI8/16)
D Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
D CLKOUT Off Control to Disable CLKOUT
D On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1(JTAG) Boundary Scan
Logic
D 144-Pin Ball Grid Array (BGA)
(GGU Suffix)
D 144-Pin Low-Profile Quad Flatpack (LQFP)
(PGE Suffix)
D 6.25-ns Single-Cycle Fixed-Point
Instruction Execution Time (160 MIPS)
D 3.3-V I/O Supply Voltage
D 1.6-V Core Supply Voltage
All trademarks are the property of their respective owners.
† Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
‡ IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.


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