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SM320VC5421-EP データシート(PDF) 10 Page - Texas Instruments |
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SM320VC5421-EP データシート(HTML) 10 Page - Texas Instruments |
10 / 95 page Introduction 2 July 2003 SGUS047 2 Introduction This section describes the main features, gives a brief functional overview of the SM320VC5421-EP, lists the pin assignments, and provides a signal description table. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging. NOTE: This data manual is designed to be used in conjunction with the TMS320C54x DSP Functional Overview (literature number SPRU307). 2.1 Description The 320VC5421 fixed-point digital signal processor (DSP) is a dual-core solution running at 200-MIPS performance. The 5421 consists of two DSP subsystems capable of core-to-core communications and a 128K-word zero-wait-state on-chip program memory shared by the two DSP subsystems. Each subsystem consists of one 54x DSP core, 32K-word program/data DARAM, 32K-word data SARAM, 2K-word ROM, three multichannel serial interfaces, xDMA logic, one timer, one APLL, and other miscellaneous circuitry. The 5421 also contains a host-port interface (HPI) that allows the 5421 to be viewed as a memory-mapped peripheral to a host processor. The 5421 is pin-compatible with the TMS320VC5420. Each subsystem has its separate program and data spaces, allowing simultaneous accesses to program instructions and data. Two read operations and one write operation can be performed in one cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. Furthermore, data can be transferred between program and data spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5421 includes the control mechanisms to manage interrupts, repeated operations, and function calls. In addition, the 5421 has 128K words of on-chip program memory that can be shared between the two subsystems. The 5421 is intended as a high-performance, low-cost, high-density DSP for remote data access or voice-over IP subsystems. It is designed to maintain the current modem architecture with minimal hardware and software impacts, thus maximizing reuse of existing modem technologies and development efforts. 2.2 Migration From the 5420 to the 5421 Customers migrating from the 5420 to the 5421 need to take into account the following: • The memory structure of the 5421 has been changed to incorporate 128K x 16-bit words of two-way shared memory. • The DMA of the 5421 has been enhanced to provide access to external, as well as internal memory. • The HPI and DMA memory maps have been changed to incorporate the new memory 5421. • 2K x 16-bit words of ROM have been added to the 5421 for bootloading purposes only. • The VCO pin on the 5420 has been replaced with the HOLDA pin on the 5421 and the HOLD pin was added to the 5421 at a previously unused pin location. • The McBSPs have been updated with a new mode that allows 128-channel selection capability. • McBSP CLKX/R pins can be used as inputs to internal clock rate generator for CLKS-like function without the penalty of extra pins. • The SELA/B pin on 5421 is changed to type I/O/Z for added functionality. NOTE: For additional information, see TMS320VC5420 to TMS320VC5421 DSP Migration (literature number SPRA621). TMS320C54x is a trademark of Texas Instruments. |
同様の部品番号 - SM320VC5421-EP |
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同様の説明 - SM320VC5421-EP |
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