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ISL267817 データシート(PDF) 11 Page - Intersil Corporation |
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ISL267817 データシート(HTML) 11 Page - Intersil Corporation |
11 / 18 page ISL267817 11 FN7877.2 April 19, 2012 Functional Description The ISL267817 is based on a successive approximation register (SAR) architecture utilizing capacitive charge redistribution digital to analog converters (DACs). Figure 25 shows a simplified representation of the converter. During the acquisition phase (ACQ), the differential input is stored on the sampling capacitors (CS). The comparator is in a balanced state since the switch across its inputs is closed. The signal is fully acquired after tACQ has elapsed, and the switches then transition to the conversion phase (CONV) so the stored voltage may be converted to digital format. The comparator will become unbalanced when the differential switch opens and the input switches transition (assuming that the stored voltage is not exactly at mid-scale). The comparator output reflects whether the stored voltage is above or below mid-scale, which sets the value of the MSB. The SAR logic then forces the capacitive DACs to adjust up or down by one quarter of full-scale by switching in binarily weighted capacitors. Again, the comparator output reflects whether the stored voltage is above or below the new value, setting the value of the next lowest bit. This process repeats until all 12 bits have been resolved. An external clock must be applied to the DCLOCK pin to generate a conversion result. The allowable frequency range for DCLOCK is 10kHz to 3.2MHz (625SPS to 200kSPS). Serial output data is transmitted on the falling edge of DCLOCK. The receiving device (FPGA, DSP or Microcontroller) may latch the data on the rising edge of DCLOCK to maximize set-up and hold times. A stable, low-noise reference voltage must be applied to the VREF pin to set the full-scale input range and common-mode voltage. See “Voltage Reference Input” on page 12 for more details. ADC Transfer Function The output coding for the ISL267817 is twos complement. The first code transition occurs at successive LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is 2*VREF/4096. The ideal transfer characteristic of the ISL267817 is shown in Figure 26. Analog Input The ISL267817 features a fully differential input with a nominal full-scale range equal to twice the applied VREF voltage. Each input swings VREF VP-P, 180° out-of-phase from one another for a total differential input of 2*VREF (refer to Figure 27). FIGURE 24. REFERENCE CURRENT vs TEMPERATURE (CODE = FF8h) Typical Performance Characteristics T A = +25°C, VCC = 5V, VREF = 2.5V, fSAMPLE = 200kHz, fCLK =16*fSAMPLE, unless otherwise specified. (Continued) 0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 TEMPERATURE (°C) FIGURE 25. SAR ADC ARCHITECTURAL BLOCK DIAGRAM +IN –IN VREF ACQ CONV ACQ ACQ CONV CONV SAR LOGIC FIGURE 26. IDEAL TRANSFER CHARACTERISTICS FIGURE 27. DIFFERENTIAL INPUT SIGNALING 1LSB = 2•VREF/4096 100...000 100...001 100...010 111...111 000...000 000...001 011...110 011...111 ANALOG INPUT +IN –(–IN) –VREF + ½LSB +VREF – 1½LSB 0V +VREF – 1LSB ISL267817 VCM VREF PP VREF PP +IN –IN |
同様の部品番号 - ISL267817 |
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同様の説明 - ISL267817 |
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