BU21049GUL

TSZ02201-0Y1Y0F300010-1-2

© 2011 ROHM Co., Ltd. All rights reserved.

31.JAN.2012 Rev.001

www.rohm.co

TSZ22111・15・001

9/23

Datasheet

Datasheet

WRITE CYCLE

The 7-bit slave address is placed in the upper of address byte and Read/Write bit is in the LSB. The BU21049GUL issue an

acknowledgement after address byte if access is correct. After received the acknowledgement, HOST can send command

byte. When HOST received an acknowledgement of command byte from BU21049GUL, HOST continuously sends a write

data byte or issues a STOP condition.

S: START condition

P: STOP condition

A: ACK

N: NACK

READ CYCLE

The LSB of address byte is READ bit. The BU21049GUL send back data byte followed by an acknowledge at read mode.

The send back data is conversion result or register value. (It’s depend on last command byte)

HOST needs to resend conversion command with setting “CMSK=1” if HOST read register value before read conversion

result. BU21049GUL send back next data byte if BU21049GUL receive the acknowledge from HOST after sending data

byte. HOST finish read access by issuing a START condition (or STOP condition) followed by a not-acknowledge(NACK)

when HOST received last data byte.

S: START condition

P: STOP condition

A: ACK

N: NACK

SCL STRETCH

If HOST read conversion result while BU21049GUL is operating conversion, the BU21049GUL notify HOST by

SCL_STRETCH function.(*1) The SCL_STRECH is released when conversion function was finished.

Convert function is running

1000001

A

C

K

Slave address & Read cycle

SCL

SDA

STATU

S

D7

D6

Stretch(SCL=L)

finish

(idle)

(*1)Force SCL to “L” after ACK of slave address.