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SN74ABT32316PN データシート(PDF) 8 Page - Texas Instruments |
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SN74ABT32316PN データシート(HTML) 8 Page - Texas Instruments |
8 / 11 page SN54ABT32316, SN74ABT32316 16BIT TRIPORT UNIVERSAL BUS EXCHANGERS SCBS179A − JUNE 1992 − REVISED JULY 1994 5−8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PARAMETER MEASUREMENT INFORMATION 1.5 V th tsu From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT FOR OUTPUTS S1 7 V Open GND 500 Ω 500 Ω Data Input Timing Input 1.5 V 3 V 0 V 1.5 V 1.5 V 3 V 0 V 3 V 0 V 1.5 V 1.5 V tw Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS PULSE DURATION tPLH tPHL tPHL tPLH VOH VOH VOL VOL 1.5 V 1.5 V 3 V 0 V 1.5 V 1.5 V Input (see Note B) 1.5 V Output Control Output Waveform 1 S1 at 7 V (see Note C) Output Waveform 2 S1 at Open (see Note C) VOL VOH tPZL tPZH tPLZ tPHZ 1.5 V 1.5 V 3.5 V 0 V 1.5 V VOL + 0.3 V 1.5 V VOH − 0.3 V [ 0 V 3 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Output Output tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7 V Open TEST S1 Output Control NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms |
同様の部品番号 - SN74ABT32316PN |
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同様の説明 - SN74ABT32316PN |
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