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M74VHCT257ADTR2G データシート(PDF) 2 Page - ON Semiconductor |
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M74VHCT257ADTR2G データシート(HTML) 2 Page - ON Semiconductor |
2 / 8 page MC74VHCT257A http://onsemi.com 2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance cir- cuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Figure 1. Pin Assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 S Y0 B0 A0 Y1 B1 A1 GND Y3 B3 A3 OE VCC B2 A2 Y2 3 OE S A0 B0 A1 B1 A2 B2 2 5 6 11 10 14 13 12 9 7 4 Y0 MUX Y1 Y2 Y3 EN 1 15 A3 B3 G1 1 1 Figure 2. IEC Logic Symbol Figure 3. Expanded Logic Diagram OE I0a I1a I0b I1b I0c I1c I0d I1d S Za Zb Zc Zd |
同様の部品番号 - M74VHCT257ADTR2G |
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同様の説明 - M74VHCT257ADTR2G |
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