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CXA3106Q データシート(PDF) 8 Page - Sony Corporation |
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CXA3106Q データシート(HTML) 8 Page - Sony Corporation |
8 / 50 page – 8 – CXA3106Q Chip select. When low, all circuits including the register circuit are set to the power save mode. When high, all circuits are set to operating mode. Register read output. When SENABLE is high, the register contents are output from SEROUT at the falling edge of SCLK. (See the Control Register Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. Programmable counter test output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. Inverted 1/2 clock output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. 1/2 clock output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. Inverted clock output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. Clock output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. Delay sync signal output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) and switched between positive/negative polarity by a control register. 14 15 16 20 21 22 23 24 CS SEROUT DIVOUT CLK/2N CLK/2 CLKN CLK DSYNC TTL TTL TTL TTL TTL TTL TTL TTL I O O O O O O O IOVCC IOGND 14 IOVCC IOGND TTLVCC TTLGND 15 20 21 22 23 24 16 100k Pin No. Symbol I/O Reference voltage level Equivalent circuit Description |
同様の部品番号 - CXA3106Q |
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同様の説明 - CXA3106Q |
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