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CXA7000R

Description of Operation

The flow of internal operations is described below.

The digital signals input to D_IN0 to D_IN9 are internally D/A converted into approximately 1.5V (at VREF_I:

3.2V) analog signals. After that, the signal that has been demultiplexed into 6 phases is amplified by a factor of

three times, inverted at the signal center potential according to FRP, and output.

The output level relative to the digital input changes according to the following settings.

A: SIG_OFST voltage

B: VREF_I voltage

C: SIG.C voltage

1. Digital input block

The CXA7000R can be set to master/slave mode, single mode and left/light inversion. This makes it possible to

support various systems.

In master/slave mode, the even and odd data is internally selected respectively and input to the D/A converter.

2. D/A converter block

The internal D/A converter has two systems for odd-numbered and even-numbered outputs. The voltage input

from VREF_I becomes the 100% white level potential of the analog converted signal, and this amplitude is a

maximum 1.5Vp-p with respect to input data of 000h to 3FFh.

3. Sample-and-hold (S/H) block

The D/A converter outputs are input to the sample-and-hold blocks, respectively. The signals are converted from

time series signals into 6-phase cyclic parallel signals by the sample-and-hold group which is appropriately

controlled by the internal timing generator. For forward scan, the signals are output in the ascending order of

SH_OUT1, SH_OUT2, SH_OUT3 ... SH_OUT6. For reverse scan, this order is inverted and the signals are

output in descending order. Connect the signals to the LCD panel according to the order used. The timing of

each sample-and-hold pulse is shown on the following pages. These pulses are not output and are used only

inside the IC.

GND

Signal Center

1023

512

0

A

A

B

B

C

Digital IN

SH_OUT